Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction

ABSTRACT

Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion paradigm between cell-level and block-level granularity, in which each layout row defines the unit of gating, and different rows can be clustered and share the same sleep transistor. Previous works, however, assume the availability of a single virtual ground voltage, thus making the decision of whether to gate or not a given cluster a binary choice: a cluster is either gated or not.

In this work, we consider a limited set of virtual ground voltages, which allows us to assign to a cluster the virtual ground voltage that offers the best leakage-performance tradeoff for that cluster. We propose two algorithms for solving two power-gating variants: one in which the entire design is gated (given an allowable delay degradation), and another one in which only a subset of the rows is gated (given an allowable delay degradation and sleep transistor area).

Our algorithm automatically finds the set of clusters with optimal virtual ground voltages so as to minimize leakage while respecting timing and area constraints. The number of power-gating domains can be user-bounded, in accordance with power grid or library characterization limitations. Results show that multiple virtual ground allow to improve by more than 34% over existing solutions that gate the entire design, and provide sizable savings also for the case of partial power-gating.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
clustering, leakage power, power-gating, row-based, sleep transistor, standard cell