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Dynamic virtual ground voltage estimation for power gating
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International Symposium on Low Power Electronics and Design archive
Proceeding of the 13th international symposium on Low power electronics and design table of contents
Bangalore, India
SESSION: Power optimization table of contents
Pages 27-32  
Year of Publication: 2008
ISBN:978-1-60558-109-5
Authors
Hao Xu  University of Cincinnati, Cincinnati, OH, USA
Ranga Vemuri  University of Cincinnati, Cincinnati, OH, USA
Wen-Ben Jone  University of Cincinnati, Cincinnati, OH, USA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

With the technology moving into the deep sub-100nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a promising technique. Our research emphasizes the virtual ground voltage (VVG) as the key to make critical design trade-offs for power gating. We develop an accurate model to estimate the dynamic VVG value of a circuit block as a function of time after its ground is gated. Experimental results show that the model has less than 1% average error compared with HSPICE results. The CAD tool implemented based on the model has a 100 times speedup over HSPICE.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Roy, K.; Mukhopadhyay, S.; Mahmoodi-Meimand, H., "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," In Proc. of the IEEE, Volume 91, pp. 305--327, Feb. 2003.
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5
Kim, S.; Choi, C. J.; Jeong, D.-K.; Kosonocky, S. V.; Park, S. B., "Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures," IEEE Trans. on Electron Devices, Volume 55, pp. 197-205, Jan. 2008.
 
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Kahng, A. B.; Muddu, S.; Sharma, P.;, "Defocus-Aware Leakage Estimation and Control," In IEEE Transactions on CAD, Volume 27, pp. 230--240, Feb. 2008.
 
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Arizona State University, "Predictive Technology Model," Available: http://www.eas.asu.edu/~ptm/
 
10
TAMU, "Layout and Parasitic Information for ISCAS Circuits," Available: http://dropzone.tamu.edu/~xiang/iscas.html

Collaborative Colleagues:
Hao Xu: colleagues
Ranga Vemuri: colleagues
Wen-Ben Jone: colleagues