Enhancing beneficial jitter using phase-shifted clock distribution

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Enhancing beneficial jitter using phase-shifted clock distribution

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International Symposium on Low Power Electronics and Design archive
Proceeding of the 13th international symposium on Low power electronics and design table of contents

Bangalore, India

SESSION: Variation tolerant circuits table of contents

Pages 21-26

Year of Publication: 2008

ISBN:978-1-60558-109-5

Authors

Dong Jiao	University of Minnesota, Minneapolis, MN, USA
Jie Gu	University of Minnesota, Minneapolis, MN, USA
Pulkit Jain	University of Minnesota, Minneapolis, MN, USA
Chris Kim	University of Minnesota, Minneapolis, MN, USA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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ABSTRACT

Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor.

REFERENCES

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