Optimal technology selection for minimizing energy and variability in low voltage applications

ABSTRACT

Ultra Low voltage operation has recently drawn significant attention due to its large potential energy savings. However, typical design practices used for super-threshold operation are not necessarily compatible with the low voltage regime. Here, radically different guidelines may be needed since existing process technologies have been optimized for super-threshold operation. We therefore study the selection of the optimal technology in ultra low voltage designs to achieve minimum energy and minimum variability which are among foremost concerns. We investigate five industrial technologies, from 250nm to 65nm. We demonstrate that mature technologies are often the best choice in very low voltage applications, saving as much as ~1800X in total energy consumption compared to a poorly selected technology. In parallel, the effect of technology choice on variability is investigated, when operating at the energy optimal design point. The results show up to a 4X improvement in delay variation due to global process shift and mismatch when using the most advanced technologies despite their large variability at nominal V_dd.

REFERENCES

• 1: M. Seok, et al, "The Phoenix Processor: A 30pW Platform for Sensor Applications", Symposium on VLSI Circuits, to be published in 2008
• 2: H. Kaul, et al, "A 320mV 56uW 411GOPS/Watt Ultra-Low-Voltage Motion-Estimation Accelerator in 65nm CMOS", ISSCC , 2008
• 3: A. Wang, et al, "A 180mV FFT Processor Using Subthreshold Circuit Techniques", ISSCC, 2004
• 4: B. Calhoun, et al, "Ultra Dynamic Voltage Scaling using Sub-Threshold Operation and Local Voltage Dithering in 90nm CMOS", ISSCC, 2005
• 5: B. Calhoun, et al, "A 256kb Sub-threshold SRAM in 65nm CMOS", ISSCC, 2006
• 6: B. Zhai, et al, "A sub-200mV 6T SRAM in 130nm CMOS", ISSCC, 2007
• 7: N. Verma, et al, "A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy", ISSCC, 2007
• 8: T. Kim, et al, "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme", ISSCC, 2007
• 9: S. Hanson, et al, "Performance and Variability Optimization Strategies in a 150mV Subthreshold Processor", Symposium on VLSI Circuits, 2007
• 10: M. Hwang, et al, "A 85mV 40nW Process-Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology", Symposium on VLSI circuits, 2007
• 11: J. Kulkarni, et al, "A 160mV Robust Schmitt Trigger Based Subthreshold SRAM", JSSC vol.42 no.10, Oct 2007
• 12: J. Kwong, et al, "A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter", ISSCC, 2008
• 13: I. Chang, et al, "A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS", ISSCC, 2008
• 14: B. Zhai, et al, "A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency", Symposium on VLSI circuits, 2006
• 15: International Technology Roadmap for Semiconductors, 2005
• 16: Bo Zhai , David Blaauw , Dennis Sylvester , Krisztian Flautner, Theoretical and practical limits of dynamic voltage scaling, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996798]
• 17: Benton H. Calhoun , Anantha Chandrakasan, Characterizing and modeling minimum energy operation for subthreshold circuits, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013265]
• 18: L. Nazhadili, et al, "SenseBench: Toward on Accurate Evaluation of Sensor Network Processors", Workload Characterization Symposium, 2005
• 19: Mingoo Seok , Scott Hanson , Dennis Sylvester , David Blaauw, Analysis and optimization of sleep modes in subthreshold circuit design, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278655]
• 20: Scott Hanson , Mingoo Seok , Dennis Sylvester , David Blaauw, Nanometer device scaling in subthreshold circuits, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278656]
• 21: B. Paul, "Device Optimization for Digital Subthreshold Logic Operation", TED vol.52 no.2, Feb 2005
• 22: D. G. Chinnery , K. Keutzer, Closing the gap between ASIC and custom: an ASIC perspective, Proceedings of the 37th conference on Design automation, p.637-642, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337602]
• 23: Bo Zhai , Scott Hanson , David Blaauw , Dennis Sylvester, Analysis and mitigation of variability in subthreshold design, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA [doi>10.1145/1077603.1077610]
• 24: Tae-Hyoung Kim , Hanyong Eom , John Keane , Chris Kim, Utilizing reverse short channel effect for optimal subthreshold circuit design, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany [doi>10.1145/1165573.1165603]
• 25: James Kao , Anantha Chandrakasan , Dimitri Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, Proceedings of the 34th annual conference on Design automation, p.409-414, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266182]
• 26: Nam Sung Kim , Krisztian Flautner , David Blaauw , Trevor Mudge, Circuit and microarchitectural techniques for reducing cache leakage power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.167-184, February 2004 [doi>10.1109/TVLSL.2003.821550]
• 27: Y. Takeyama, et al, "A Low Leakage SRAM Macro with Replica Cell Biasing Scheme", JSCC vol.41 no.4, April 2006
• 28: A. Agarwal, et al, "A single-Vt Low-Leakage Gated-Grounded Cache for Deep Submicron", JSSC vol 38 no.2, Feb 2003
• 29: Chris H. Kim , Kaushik Roy, Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566473]
• 30: Chris H. Kim , Jae-Joon Kim , Saibal Mukhopadhyay , Kaushik Roy, A forward body-biased low-leakage SRAM cache: device and architecture considerations, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871511]
• 31: Shekhar Borkar, Low power design challenges for the decade (invited talk), Proceedings of the 2001 conference on Asia South Pacific design automation, p.293-296, January 2001, Yokohama, Japan [doi>10.1145/370155.370356]
• 32: Gregory K. Chen , David Blaauw , Trevor Mudge , Dennis Sylvester , Nam Sung Kim, Yield-driven near-threshold SRAM design, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
• 33: Joyce Kwong , Anantha P. Chandrakasan, Variation-driven device sizing for minimum energy sub-threshold circuits, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany [doi>10.1145/1165573.1165578]
• 34: M.J.M. Pelgrom, et al., "Matching properties of MOS transistors", JSSC vol.24, no.5, 1989
• 35: V. Verma, et al, "Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits", TED vol.55 no.1, Jan 2008

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design

Keywords:
low voltage operation, optimal technology