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System implications of integrated photonics
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Source
International Symposium on Low Power Electronics and Design archive
Proceeding of the 13th international symposium on Low power electronics and design table of contents
Bangalore, India
Pages: 183-184  
Year of Publication: 2008
ISBN:978-1-60558-109-5
Author
Norman P. Jouppi  Hewlett-Packard, Palo Alto, CA, USA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Micron-scale photonic devices integrated with standard CMOS processes have the potential to dramatically increase system bandwidths, performance, and configuration flexibility while reducing system power. I first describe some recent developments in silicon nanophotonic technology, such as microring resonators. Small devices have many advantages: reduced power, increased density, and increased speed. By integrating many thousands of these devices on a chip, photonics could potentially be used for most high-speed off-chip and global on-chip communication.

Integrated photonics has many advantages at the board and rack scale as well. Recent high-speed board-level electrical signaling (>2.5GHz) precludes the use of multi-drop busses or communication over long distances on ordinary inexpensive PC board materials. By using photonics, high fan-out and high-fan-in bus structures can be built. Due to the low loss of optical signals versus distance, these structures can even be distributed over rack-scale distances. This dramatically increases system flexibility while reducing interconnect power.

As an example of the potential impact of photonics, I describe a system architecture for the 2017 time frame we call Corona. Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We believe that in comparison with an electrically-connected many-core alternative, Corona can provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously significantly reducing power.