On the trade-off between power and flexibility of FPGA clock networks

ABSTRACT

FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This article examines the trade-off between the power consumption and flexibility of FPGA clock networks.

Specifically, this article makes three contributions. First, it presents a new parameterized clock-network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement satisfying the constraints imposed by the clock network. Finally, it performs an empirical study to examine the trade-off between the power consumption of the clock network and the impact of the CAD constraints for a number of different clock networks with varying amounts of flexibility.

The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5% less overall energy and are significantly more likely to be legal than circuits placed using other techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network are up to 14.6% more energy efficient compared to other FPGAs.

REFERENCES

• 1: ACTEL. 2007. ProASIC3 flash family FPGAs datasheet: Device architecture (Jan.).
• 2: ALTERA. 2005. Stratix II Device Handbook 1. Chapter 2 (Mar.).
• 3: ALTERA. 2006. Stratix III Device Handbook 1. Chapter 6 (Nov.).
• 4: Bakolgu, H. B. 1990. Machine organization and rent's rule. In Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading, MA.
• 5: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 6: Brynjolfson, I. and Zilic, Z. 2000. Dynamic clock management for low-power applications in FPGAs. In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 139--142.
• 7: Masato Edahiro , Richard J. Lipton, Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model, Proceedings of the 6th Great Lakes Symposium on VLSI, p.143, March 22-23, 1996
• 8: Friedman, E. G. 2001. Clock distribution networks in synchronous digital integrated circuits. Proc. IEEE 89, 5 (May), 665--692.
• 9: Varghese George , Hui Zhang , Jan Rabaey, The design of a low energy FPGA, Proceedings of the 1999 international symposium on Low power electronics and design, p.188-193, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313920]
• 10: Lamoureux, J., and Wilton, S. J. E. 2005. On the interaction between power-aware computer-aided design algorithms for field-programmable gate arrays. J. Low Power Electron. 1, 2, 119--132.
• 11: Julien Lamoureux , Steven J. E. Wilton, FPGA clock network architecture: flexibility vs. area and power, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA [doi>10.1145/1117201.1117216]
• 12: Lamoureux, J. and Wilton, S. J. E. 2007. Clock-Aware placement for FPGAs. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL).
• 13: B. S. Landman , R. L. Russo, On a Pin Versus Block Relationship For Partitions of Logic Graphs, IEEE Transactions on Computers, v.20 n.12, p.1469-1479, December 1971 [doi>10.1109/T-C.1971.223159]
• 14: Fei Li , Deming Chen , Lei He , Jason Cong, Architecture evaluation for power-efficient FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611844]
• 15: S. Nakamura , G. M. Masson, Lower Bounds on Crosspoints in Concentrators, IEEE Transactions on Computers, v.31 n.12, p.1173-1179, December 1982 [doi>10.1109/TC.1982.1675941]
• 16: Kara K. W. Poon , Steven J. E. Wilton , Andy Yan, A detailed power model for field-programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.279-302, April 2005 [doi>10.1145/1059876.1059881]
• 17: V. Natesan , D. Bhatia, Clock-Skew Constrained Cell Placement, Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, p.146, January 03-06, 1996
• 18: Karl Schabas , Stephen D. Brown, Using logic duplication to improve performance in FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611838]
• 19: Tim Tuan , Sean Kao , Arif Rahman , Satyaki Das , Steve Trimberger, A 90nm low-power FPGA for battery-powered applications, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA [doi>10.1145/1117201.1117203]
• 20: XILINX. 2007. Virtex-5 User Guide. Chapter 2 (Feb).
• 21: Zhu, K. and Wong, D. F. 1997. Clock skew minimization during FPGA placement. IEEE Trans. Comput. Aided Des. Integr. Circ. 16, 4 (Apr.), 376--385.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Experimentation

Keywords:
FPGA, clock distribution networks, clock-aware placement, low-power design