Leakage power reduction using stress-enhanced layouts

ABSTRACT

In recent years, process-induced mechanical stress has emerged as a useful manufacturing technique that enhances carrier transport and increases drive currents. This improvement in current has helped to compensate the decline of device scaling factors in parameters such as t_ox, V_th, and V_dd. In this work, we propose stress as a means to achieve optimal power-performance trade-off by combining stress-based, performance-enhanced standard cell assignment with dual-V_th assignment. We study how stress-induced performance enhancements are affected by layout properties and improve standard cell layouts so that performance gains are maximized. We then develop a circuit-level, block-based, stress-enhanced optimization algorithm that includes all layout-dependent sources of mechanical stress. By combining the two performance enhancement techniques (stress-based and dual-V_th) for a set of benchmark circuits, we find that our stress-aware optimization, decreases leakage by ~24% on average, for iso-delay, when compared to dual-V_th assignment. Similarly, for iso-leakage, our optimization algorithm reduces delay on average by 5%. In both cases, the proposed method only incurs a small area penalty (< 0.5%).

REFERENCES

• 1: F. Andrieu et al., "Experimental and Comparative Investigation of Low and High Field Transport in Substrate- and Process-Induced Strained Nanoscale MOSFETs," in Proc. VLSI Tech. Symp. Tech. Dig., pp. 176--177, 2005.
• 2: K. Mistry et al., "Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology," in Proc. VLSI Technol. Symp. Tech. Dig., pp. 50--51, 2005.
• 3: S. Wolf, "Silicon Processing for the VLSI Era," Lattice Press, 1995.
• 4: Anantha P. Chandrakasan , William J. Bowhill , Frank Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE Press, 2000
• 5: Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Rajendran Panda , David Blaauw, Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.79-90, April 2002 [doi>10.1109/92.994980]
• 6: Liqiong Wei , Zhanping Chen , Mark Johnson , Kaushik Roy , Vivek De, Design and optimization of low voltage high performance dual threshold CMOS circuits, Proceedings of the 35th annual conference on Design automation, p.489-494, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277179]
• 7: D. Sylvester and A. Srivastava, "Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS,", in Proc. of the IEEE, Vol. 95, pp. 507--529, March 2007.
• 8: R. A. Bianchi et al., "Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance," in Proc. IEDM, pp. 117--120, 2002.
• 9: Andrew B. Kahng , Puneet Sharma , Rasit O. Topaloglu, Exploiting STI stress for performance, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
• 10: V. Moroz et al., "The Impact of Layout on Stress-Enhanced Transistor Performance," in Proc. SISPAD, pp. 143--146, 2005.
• 11: M. V. Dunga et al., "Modeling Advanced FET Technology in a Compact Model," in IEEE Trans. on Elect. Dev., Vol. 53, No. 9, pp. 1971--1978, September 2006.
• 12: Vivek Joshi , Brian Cline , Dennis Sylvester , David Blaauw , Kanak Agarwal, Stress aware layout optimization, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA [doi>10.1145/1353629.1353666]
• 13: V. Chan et al., "Strain for PMOS performance Improvement," in Proc. CICC, pp. 667--674, 2005.
• 14: W. H. Lee et al., "High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL," in Proc. IEDM, 2005.
• 15: H. S. Yang et al., "Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing," in Proc. IEDM, pp. 1075--1077, 2004.
• 16: K. Ota et al., "Novel locally strained channel technique for high performance 55nm CMOS," in Proc. IEDM, pp. 27--30, 2002.
• 17: Z. Luo et al., "Design of high performance PFETs with strained si channel and laser anneal," in Proc. IEDM, pp. 489--492, 2005.
• 18: Manual, Davinci 3D TCAD, Version 2005.10.
• 19: Manual, Synopsys TSUPREM4, Version 2007.03.
• 20: J. Dunning, Transistor-Level Sizing and Timing Verification of Domino Circuits in the Power PC(TM) Microprocessor, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.143, October 12-15, 1997
• 21: Victor Zyuban , Philip Strenski, Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566451]
• 22: Steven M. Burns , Mahesh Ketkar , Noel Menezes , Keith A. Bowman , James W. Tschanz , Vivek De, Comparative analysis of conventional and statistical design techniques, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278539]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.0 General

General Terms:
Performance

Keywords:
layout, leakage, mobility, performance, stress