Automated transistor sizing for FPGA architecture exploration

ABSTRACT

The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and routing architectures are considered. For such explorations, it is not feasible to spend significant amounts of time on transistor-level design. This paper presents an automated transistor sizing tool for FPGA architecture exploration that uses a two-phased approach - a coarse rapid phase with simple modeling followed by refinement with much more accurate models. The output of the system is a design optimized towards a specific area-delay criterion. We compare the quality of our results to prior manual and partially automated approaches. Also, our tool has been used to produce hundreds of candidate architectures which we are releasing to support future high quality explorations.

REFERENCES

• 1: E. Ahmed and J. Rose. The effect of LUT and cluster size on deep-submicron FPGA performance and density. TVLSI, 12(3):288--298, March 2004.
• 2: Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997
• 3: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 4: A. R. Conn , I. M. Elfadel , W. W. Molzen, Jr. , P. R. O'Brien , P. N. Strenski , C. Visweswariah , C. B. Whan, Gradient-based optimization of custom circuits using a static-timing formulation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.452-459, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309979]
• 5: J. P. Fishburn and A. Dunlop. TILOS: A posynomial programming approach to transistor sizing. In ICCAD, pages 326--328, Nov. 1985.
• 6: E. Lee et al. Interconnect driver design for long wires in FPGAs. In FPT, pages 89--96, Dec. 2006.
• 7: G. Lemieux et al. Directional and single-driver wires in FPGA interconnect. In FPT, pages 41--48, Dec. 2004.
• 8: David Lewis , Elias Ahmed , Gregg Baeckler , Vaughn Betz , Mark Bourgeault , David Cashman , David Galloway , Mike Hutton , Chris Lane , Andy Lee , Paul Leventis , Sandy Marquardt , Cameron McClintock , Ketan Padalia , Bruce Pedersen , Giles Powell , Boris Ratchev , Srinivas Reddy , Jay Schleicher , Kevin Stevens , Richard Yuan , Richard Cliff , Jonathan Rose, The Stratix II logic and routing architecture, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA [doi>10.1145/1046192.1046195]
• 9: John K. Ousterhout, Switch-level delay models for digital MOS VLSI, Proceedings of the 21st conference on Design automation, p.542-548, June 25-27, 1984, Albuquerque, New Mexico, United States
• 10: J. Rubinstein et al. Signal delay in RC tree networks. TCAD, 2(3):202--211, July 1983.
• 11: S. S. Sapatnekar et al. An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. TCAD, 12(11):1621--1634, 1993.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Measurement

Keywords:
FPGA, optimization, transistor sizing