An integrated nonlinear placement framework with congestion and porosity aware buffer planning

ABSTRACT

Due to skewed scaling of interconnect versus cell delay in deep submicron CMOS, modern VLSI timing closure requires extensive buffer insertion. Inserting a large number of buffers may cause not only dramatic cell migration but also routing hotspots. If buffering is not controlled well, it may fail to close a design. Placement with buffer porosity (i.e., cell density) awareness can allocate space for inserting these buffers, and buffering with congestion awareness can improve the routability. Therefore, there is essential need for a placement framework with explicit porosity and congestion control. In this paper, we propose the first integrated nonlinear placement framework with porosity and congestion aware buffer planning. We demonstrate the integration of increasingly refined cell porosity and routing congestion aware buffer planning and insertion methodology in a high quality nonlinear placer. Our experiments show the improvement of average routing overflow by 69%, average wirelength by 28% and average buffer count by 40%, compared with the traditional placement framework without buffer planning.

REFERENCES

• 1: IWLS 2005 Benchmarks. http://iwls.org/iwls2005/benchmarks.html.
• 2: OpenAccess. http://www.si2.org/.
• 3: OpenAccess Gear. http://openedatools.si2.org/oagear/.
• 4: OpenCores. http://www.opencores.org/.
• 5: Charles Alpert , Andrew Kahng , Gi-Joon Nam , Sherief Reda , Paul Villarrubia, A semi-persistent clustering technique for VLSI circuit placement, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA [doi>10.1145/1055137.1055179]
• 6: Tung-Chieh Chen , Zhe-Wei Jiang , Tien-Chang Hsu , Hsin-Chen Chen , Yao-Wen Chang, A high-quality mixed-size analytical placer considering preplaced blocks and density constraints, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233538]
• 7: Chris Chu , Yiu-Chung Wong, Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA [doi>10.1145/1055137.1055145]
• 8: Jason Cong , Tianming Kong , Zhigang (David) Pan, Buffer block planning for interconnect planning and prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.929-937, 12/1/2001 [doi>10.1109/92.974906]
• 9: Brent Goplen , Prashant Saxena , Sachin Sapatnekar, Net weighting to reduce repeater counts during placement, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065710]
• 10: Ali Jahanian , Morteza Saheb Zamani, Improved timing closure by early buffer planning in floor-placement design flow, Proceedings of the 17th ACM Great Lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy [doi>10.1145/1228784.1228916]
• 11: A. B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. IEEE Trans. Computer-Aided Design, 24(5), May 2005.
• 12: J. Lou, S. Thakur, S. Krishnamoorthy, and H. S. Sheng. Estimating routing congestion using probabilistic analysis. IEEE Trans. Computer-Aided Design, 21(1): 32--41, Jan. 2002.
• 13: L. Luo, Q. Zhou, Y. Cai, X. Hong, and Y. Wang. A novel techniqure integrating buffer insertion into timing driven placement. In Proc. IEEE Int. Symp. on Circuits and Systems, Island of Kos, Greece, May 2006.
• 14: W. C. Naylor, R. Donelly, and L. Sha. US patent 6,301,693: Non-linear optimization system and method for wire length and dealy optimization for an automatic electric circuit placer. 2001.
• 15: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 16: Prashant Saxena , Bill Halpin, Modeling repeaters explicitly within analytical placement, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996759]
• 17: P. Saxena, N. Menezes, P. Cocchini, and D. Kirkpatrick. Repeater scaling and its impact on cad. IEEE Trans. Computer-Aided Design, 23(4): 451--463, 2004.
• 18: Jurjen Westra , Chris Bartels , Patrick Groeneveld, Probabilistic congestion prediction, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA [doi>10.1145/981066.981110]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
VLSI, buffer, physical design, placement