| Design and CAD for 3D integrated circuits |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 45th annual Design Automation Conference
table of contents
Anaheim, California
SESSION: Special session: 3-D semiconductor integration & packaging
table of contents
Pages 668-673
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
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Authors
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Paul D. Franzon
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NC State University, ECE, Raleigh, NC
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W. Rhett Davis
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NC State University, ECE, Raleigh, NC
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Michael B. Steer
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NC State University, ECE, Raleigh, NC
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Steve Lipa
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NC State University, ECE, Raleigh, NC
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Eun Chu Oh
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NC State University, ECE, Raleigh, NC
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Thor Thorolfsson
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NC State University, ECE, Raleigh, NC
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Samson Melamed
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NC State University, ECE, Raleigh, NC
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Sonali Luniya
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NC State University, ECE, Raleigh, NC
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Tad Doxsee
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PTC Inc, Needham, MA
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Stephen Berkeley
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PTC Inc, Needham, MA
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Ben Shani
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PTC Inc, Needham, MA
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Kurt Obermiller
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PTC Inc, Needham, MA
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Downloads (6 Weeks): 26, Downloads (12 Months): 161, Citation Count: 0
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ABSTRACT
High density Through Silicon Vias (TSV) can be used to build 3DICs that enable unique applications in computing, signal processing and memory intensive systems. This paper presents several case studies that are uniquely enhanced through 3D implementation, including a 3D CAM, an FFT processor, and a SAR processor. The CAD flow used to implement for these designs is described. 3DIC requires higher fidelity thermal modeling than 2DIC design. The rationale for this requirement is established and a possible solution is presented.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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W. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. Sule, M. Steer, and P. D. Franzon, "Demystifying 3D ICs: The Pros and Cons of Going Veritical," IEEE Design and Test of Computers, VOl. 222, No. 6, Nov-Dec, 2005, pp. 498--510. Bowman, M., Debray, S. K., and Peterson, L. L. 1993
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E. C. Oh, P. D. Franzon, "Design Considerations and benefits of Three-Dimensional Temary Content Addressable Memory," Proc. IEEE CICC, Oct., 2007.
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H. Hua, "Design and Verification Methodology for Complex Three-Dimensional Digital Integrated Circuits," Ph.D. Dissertation, NC State University, 2006.
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K. Schoenfliess, "Performance Analsysi of System-on-Chip Application of 3D Integrated Circuits," MS. Thesis, NC State University.
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H. P Hofstee, "Future Microprocessors and off-chip SOP Interconnect," in IEEE Trans. Advanced Packaging, Vol. 27, No. 2, May 2004, pp. 301--303.
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P. Li, et al., "IC thermal simulation and modeling via efficient multigrid-based approaches." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, Vol. 25, pp. 1763--1776.
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E. Richard, et al., "Manufacturability and Speed Performance Demonstration of Porous ULK (k=2.5) for a 45nm CMOS Platform." 2007. pp. 178--17.
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