Tera-scale computing and interconnect challenges

ABSTRACT

Future CPU directions are increasingly emphasizing parallel compute platforms which are critically dependent upon upon greater core to core communication as well as generally stressing the overall memory and storage interconnect hierarchy to a much greater degree than extrapolations of past platform needs. Performance is critically dependent upon memory bandwidth and latency but must be moderated with power and cost considerations. 3D stacking of CPU's and memory (i.e. a last level cache) is a potential solution that provides the necessary bandwidth within a reasonable power envelope.

REFERENCES

• 1: J. Hurley., "Ray Tracing Goes Mainstream", ITJ, Vol 09, pp 99--107, May 2005
• 2: S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Schanz, D. Finan, P. Iyer, A Singh, T. Jacob, S. Jairr, S. Venkataramarr, Y. Hoskote, N. Borkar, "An 80 Tile 1.28 TFLOPs Network-on-Chip in 65 nm CMOS", Paper 5.2, ISSCC 2006, San Francisco.
• 3: W. Holt, Hot Chips 17 Keynote, August 2005
• 4: P. R. Morrow, C. M. Park. S. Ramanathan, M. J. Kobrinsky, and M. Harmes, "Three-dimensional Wafer Stacking via Cu-Cu Bonding Integrated with 65 nm Strained Si/Low-k CMOS Technology", IEEE Electron Device Letters, Vol 27, No 5, May 2006, pp 335--337.
• 5: P. R. Morrow, B. Black, M. J. Kobrinsky, S. Muthukumar, D. Nelson, C-M. Park, C. Webb, "Design and Fabrication of 3D Microprocessors", in Enabling Technologies for 3-D Integration, edited by Christopher A. Bower, Philip E. Garrou, Peter Ramm, and Kenji Takahashi (Mater. Res. Soc. Symp. Proc. 970, Warrendale, PA, 2007), paper 0970-Y03--02.
• 6: Bryan Black , Murali Annavaram , Ned Brekelbaum , John DeVale , Lei Jiang , Gabriel H. Loh , Don McCaule , Pat Morrow , Donald W. Nelson , Daniel Pantuso , Paul Reed , Jeff Rupley , Sadasivan Shankar , John Shen , Clair Webb, Die Stacking (3D) Microarchitecture, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.469-479, December 09-13, 2006 [doi>10.1109/MICRO.2006.18]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Asynchronous/synchronous operation

General Terms:
Design, Economics, Experimentation, Reliability

Keywords:
die stacking, many core, parallel computing