Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification

ABSTRACT

In this paper, a methodology for full-chip leakage analysis based on accurate modeling of different leakage currents in nano-scaled MOSFETs has been developed. Novel process effects have been covered in our statistical model, and a systematic characterization method of leakage-related parameter variations has been proposed. With these two contributions, we present an effective algorithm to address the growing issue of full-chip leakage verification for actual-fabrication circuits. Unlike many traditional approaches that rely on log-Normal approximations, the proposed algorithm applies a quadratic model of the logarithm for the full-chip leakage current and is able to include both Gaussian and Non-Gaussian parameter distributions. Our simulation examples in a 65nm CMOS process demonstrate that the proposed methodology provides more accurate results compared with the previous methods, while achieving orders of magnitude more efficiency than a Monte Carlo analysis.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance, Reliability

Keywords:
leakage modeling, statistical analysis, variation source