| An efficient incremental algorithm for min-area retiming |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 45th annual Design Automation Conference
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Anaheim, California
SESSION: Advances in sequential optimization
table of contents
Pages 528-533
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
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Authors
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Jia Wang
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Northwestern University, Evanston, IL
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Hai Zhou
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Northwestern University, Evanston, IL
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Downloads (6 Weeks): 4, Downloads (12 Months): 39, Citation Count: 1
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ABSTRACT
As one of the most effective sequential optimization techniques, retiming is a structural transformation that relocates flip-flops in a circuit without changing its functionality. The min-area retiming problem seeks a solution with the minimum flip-flop area (or number) under a given clock period. Even though having polynomial runtime, the best existing algorithms for this problem still need to first construct a dense path graph and then find a min-cost network flow on it, thus incur huge storage and time expenses for large circuits. Recently, provable incremental algorithms have been discovered for min-period retiming, and heuristic incremental algorithms have been proposed for min-area retiming. However, given the complexity of the problem, min-area retiming is still resisting an efficient provable incremental algorithm. In this paper, we fill the gap by presenting an efficient algorithm to solve the min-area retiming problem incrementally and optimally. Contrary to existing approaches, no dense path graph is constructed; only the active timing constraints are dynamically generated in the algorithm. Experimental results show that the total runtime of our algorithm for all the benchmarks is at least 60 x faster than the best existing approach.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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