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An efficient incremental algorithm for min-area retiming
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 45th annual Design Automation Conference table of contents
Anaheim, California
SESSION: Advances in sequential optimization table of contents
Pages 528-533  
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
Authors
Jia Wang  Northwestern University, Evanston, IL
Hai Zhou  Northwestern University, Evanston, IL
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: IEEE/CASS/CANDE/CEDA
: The EDA Consortium
Publisher
ACM  New York, NY, USA
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ABSTRACT

As one of the most effective sequential optimization techniques, retiming is a structural transformation that relocates flip-flops in a circuit without changing its functionality. The min-area retiming problem seeks a solution with the minimum flip-flop area (or number) under a given clock period. Even though having polynomial runtime, the best existing algorithms for this problem still need to first construct a dense path graph and then find a min-cost network flow on it, thus incur huge storage and time expenses for large circuits. Recently, provable incremental algorithms have been discovered for min-period retiming, and heuristic incremental algorithms have been proposed for min-area retiming. However, given the complexity of the problem, min-area retiming is still resisting an efficient provable incremental algorithm. In this paper, we fill the gap by presenting an efficient algorithm to solve the min-area retiming problem incrementally and optimally. Contrary to existing approaches, no dense path graph is constructed; only the active timing constraints are dynamically generated in the algorithm. Experimental results show that the total runtime of our algorithm for all the benchmarks is at least 60 x faster than the best existing approach.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
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G. Even, I. Y. Spillinger, L. Stok. Retiming revisited and reversed. IEEE TCAD, 15(3):348--357, Mar. 1996.
 
3
D. S. Hochbaum. A new---old algorithm for minimum-cut and maximum-flow in closure graphs. Networks, 37(4):171--193, Jul. 2001.
 
4
 
5
C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1):5--35, 1991.
 
6
H. Lerchs and I. F. Grossmann. Optimum design of open-pit mines. Trans C.I.M., 68:17--24, 1965.
7
 
8
N. Maheshwari and S. S. Sapatnekar. Efficient retiming of large circuits. IEEE TVLSI, 6(1):74--83, Mar. 1998.
 
9
S. S. Sapatnekar and R. B. Deokar. Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. IEEE TCAD, 15(10):1237--1248, Oct. 1996.
 
10
11
 
12
H. J. Touati, R. K. Brayton. Computing the initial states of retimed circuits. IEEE TCAD, 12(1):157--162, Jan. 1993.
13
 
14
Berkeley Logic Synthesis and Verification Group. ABC---a system for sequential synthesis and verification. http://www.eecs.berkeley.edu/~alanmi/abc/.
 
15
CAD Group at Politecnico di Torino. ITC '99 benchmarks (2nd release). http://www.cad.polito.it/tools/itc99.html.
 
16
CS2 version 4.3. Andrew Goldberg's network optimization library. http://www.avglab.com/andrew/soft.html.