A "true" electrical cell model for timing, noise, and power grid verification

ABSTRACT

Empirically characterized equation- and table-based cell models have been applied in static timing analysis for decades. These models have been extended to handle a variety of environmental and circuit phenomena over the years. This has given rise to a profusion of cell models that are used to verify circuit functionality and performance. The recent invention of a second-generation of current source models shows the promise of a unified electrical cell model that comprehensively addresses most of the effects that are perceived as accuracy limiters. In this paper, we describe these accuracy limiters and present comprehensive results for a particular current source model [11].

REFERENCES

• 1: Chandu Visweswariah, Death, taxes and failing chips, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775921]
• 2: David Blaauw , Supamas Sirichotiyakul , Chanhee Oh, Driver modeling and alignment for worst-case delay noise, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.157-166, April 2003 [doi>10.1109/TVLSI.2002.808448]
• 3: Dionysios Kouroussis , Rubil Ahmadi , Farid N. Najm, Worst-case circuit delay taking into account power supply variations, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996745]
• 4: F. Dartu, N. Menezes, and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Trans. on CAD, vol. 15, no. 5, pp. 544--553, May 1996.
• 5: John F. Croix , D. F. Wong, Blade and razor: cell and interconnect delay analysis using current-based models, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775933]
• 6: I. Keller , Ken Tseng , N. Verghese, A robust cell-level crosstalk delay change analysis, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.147-154, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382562]
• 7: Peng Li , Emrah Acar, A Waveform Independent Gate Model for Accurate Timing Analysis, Proceedings of the 2005 International Conference on Computer Design, p.363-365, October 02-05, 2005 [doi>10.1109/ICCD.2005.17]
• 8: Chirayu Amin , Chandramouli Kashyap , Noel Menezes , Kip Killpack , Eli Chiprout, A multi-port current source model for multiple-input switching effects in CMOS library cells, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146974]
• 9: V. Veetil, D. Sylvester, and D. Blaauw, "Fast and accurate waveform analysis with current source models," TAU workshop presentation, Feb. 2007.
• 10: Hanif Fatemi , Shahin Nazarian , Massoud Pedram, A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms, Proceedings of the 2007 conference on Asia South Pacific design automation, p.774-779, January 23-26, 2007 [doi>10.1109/ASPDAC.2007.358083]
• 11: Chandramouli Kashyap , Chirayu Amin , Noel Menezes , Eli Chiprout, A nonlinear cell macromodel for digital applications, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
• 12: Florentin Dartu , Lawrence T. Pileggi, Calculating worst-case gate delays due to dominant capacitance coupling, Proceedings of the 34th annual conference on Design automation, p.46-51, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266033]
• 13: Chirayu S. Amin , Florentin Dartu , Yehea I. Ismail, Weibull Based Analytical Waveform Model, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.161, November 09-13, 2003 [doi>10.1109/ICCAD.2003.150]
• 14: S. R. Nassif and E. Acar, "Advanced waveform models for the nanometer regime," TAU workshop presentation, 2004.
• 15: V. Chandramouli , Karem A. Sakallah, Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time, Proceedings of the 33rd annual conference on Design automation, p.617-622, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240635]
• 16: Liang-Chi Chen , Sandeep K. Gupta , Melvin A. Breuer, A new gate delay model for simultaneous switching and its applications, Proceedings of the 38th conference on Design automation, p.289-294, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378488]
• 17: F. Dartu, K. Killpack, C. Amin, and N. Menezes, "Evaluating the factors influencing timing accuracy," TAU workshop presentation, Feb. 2005.
• 18: J. Qian, S. Pullela, and L. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. on CAD, vol. 13, no. 12, pp. 1526--1535, Dec. 1994.
• 19: "CCS timing white paper," Composite Current Source, Synopsys, {online}, http://www.synopsys.com/products/solutions/galaxy/ccs/cc_source.html, 2005.
• 20: "Delay calculation meets the nanometer era," Cadence Technical Paper, {online} http://www.cadence.com/products/digital_ic/tech_info.aspx, 2005.
• 21: B. Tutuianu, R. Baldick, and M. S. Johnstone, "Nonlinear driver models for timing and noise analysis," IEEE Trans, on CAD, vol. 23, no. 11, pp. 1510--1521, Nov. 2004.
• 22: M. Rewienski and J. White, "A trajectory piece-wise linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices," IEEE Trans. on CAD, vol. 22, no. 2, pp. 155--170, 2003.
• 23: Ning Dong , Jaijeet Roychowdhury, Automated nonlinear Macromodelling of output buffers for high-speed digital applications, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065598]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design

Keywords:
cell models, current source models, static timing analysis