Design of a mask-programmable memory/multiplier array using G4-FET technology

ABSTRACT

A G4-FET is a 4 gate transistor that combines both JFET and MOS characteristics in a single device that may be fabricated in a standard silicon-on-insulator (SOI) process. In doing so, it enables the conducting channel to be controlled vertically through MOS gates, as well as horizontally, through junction gates. Further, depending upon how it is biased, a single G4-FET can serve as either a not-majority logic gate or as a charge storage-based memory cell. This unique device offers tremendous potential for innovative gate arrays, where real estate can be traded-off between logic and memory functions. In this paper, we take a first look at a mask-programmable G4-FET array that depending upon metal personalization, can function either as a DRAM array or a multiplier.

REFERENCES

• 1: B. Dufrene, K. Akarvardar, S. Cristoloveanu, B. J. Blalock, P. Gentil, E. Kolawa, and M. M. Mojarradi. Investigation of the four-gate action in g4-fets. ACM Trans. Elec. Dev., 51(11):1931--1935, November 2004.
• 2: Semiconductor Industries Association. International technology roadmap for semiconductors. Technical report, 2006.
• 3: Rui Zhang , Pallav Gupta , Niraj K. Jha, Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies, Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, p.229-234, January 03-07, 2005 [doi>10.1109/ICVD.2005.157]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design

Keywords:
G4-FET, gate array