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Characterizing chip-multiprocessor variability-tolerance
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 45th annual Design Automation Conference table of contents
Anaheim, California
SESSION: Analytical modeling and simulation of complex processing systems table of contents
Pages 313-318  
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
Authors
Sebastian Herbert  Carnegie Mellon University, Pittsburgh, PA
Diana Marculescu  Carnegie Mellon University, Pittsburgh, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: IEEE/CASS/CANDE/CEDA
: The EDA Consortium
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 13,   Downloads (12 Months): 60,   Citation Count: 1
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ABSTRACT

Spatially-correlated intra-die process variations result in significant core-to-core frequency variations in chip-multiprocessors. An analytical model for frequency island chip-multiprocessor throughput is introduced. The improved variability-tolerance of FI-CMPs over their globally-clocked counterparts is quantified across a range of core counts and sizes under constant die area. The benefits are highest for designs consisting of many small cores, with the throughput of a globally-clocked design with 70 small cores increasing by 8.8% when per-core frequency islands are used. The small-core FI-CMP also loses only 7.2% of its nominal performance to process variations, the least among any of the designs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Y. Abulafia and A. Kornfeld. Estimation of FMAX and ISB in microprocessors. IEEE Transactions on VLSI Systems, 13(10):1205--1209, Oct 2006.
 
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K. Bowman, S. Duvall, and J. Meindl. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE Journal of Solid-State Circuits, 37(2), Feb 2002.
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H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki. Challenge: Variability characterization and modeling for 65- to 90-nm processes. In CICC '2005: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.
 
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S. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas. VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions on Semiconductor Manufacturing, 21(1), 2008.
 
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Collaborative Colleagues:
Sebastian Herbert: colleagues
Diana Marculescu: colleagues