| Characterizing chip-multiprocessor variability-tolerance |
| Full text |
Pdf
(617 KB)
|
| Source
|
Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 45th annual Design Automation Conference
table of contents
Anaheim, California
SESSION: Analytical modeling and simulation of complex processing systems
table of contents
Pages 313-318
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 16, Downloads (12 Months): 63, Citation Count: 1
|
|
|
ABSTRACT
Spatially-correlated intra-die process variations result in significant core-to-core frequency variations in chip-multiprocessors. An analytical model for frequency island chip-multiprocessor throughput is introduced. The improved variability-tolerance of FI-CMPs over their globally-clocked counterparts is quantified across a range of core counts and sizes under constant die area. The benefits are highest for designs consisting of many small cores, with the throughput of a globally-clocked design with 70 small cores increasing by 8.8% when per-core frequency islands are used. The small-core FI-CMP also loses only 7.2% of its nominal performance to process variations, the least among any of the designs.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Y. Abulafia and A. Kornfeld. Estimation of FMAX and ISB in microprocessors. IEEE Transactions on VLSI Systems, 13(10):1205--1209, Oct 2006.
|
| |
2
|
K. Bowman, S. Duvall, and J. Meindl. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE Journal of Solid-State Circuits, 37(2), Feb 2002.
|
 |
3
|
Keith A. Bowman , Alaa R. Alameldeen , Srikanth T. Srinivasan , Chris B. Wilkerson, Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
[doi> 10.1145/1283780.1283792]
|
 |
4
|
|
 |
5
|
Nikolaos Hardavellas , Stephen Somogyi , Thomas F. Wenisch , Roland E. Wunderlich , Shelley Chen , Jangwoo Kim , Babak Falsafi , James C. Hoe , Andreas G. Nowatzyk, SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture, ACM SIGMETRICS Performance Evaluation Review, v.31 n.4, p.31-34, March 2004
[doi> 10.1145/1054907.1054914]
|
| |
6
|
|
 |
7
|
|
| |
8
|
H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki. Challenge: Variability characterization and modeling for 65- to 90-nm processes. In CICC '2005: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.
|
| |
9
|
S. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas. VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions on Semiconductor Manufacturing, 21(1), 2008.
|
| |
10
|
|
|