Statistical waveform and current source based standard cell models for accurate timing analysis

ABSTRACT

Increasing variability in the manufacturing process and growing complexity of the integrated circuits has given rise to many design and verification challenges. Statistical analysis of circuits and current source based gate delay models have started to replace the conventional static timing analysis which uses lookup tables for gate delays. In this paper we develop a statistical current source based gate model. We use accurate analytical models for representing the parameters of the gate model as functions of process parameters. Using the proposed statistical gate model, the gate output signal is generated and modeled as process dependent variational waveform. We present a compact model for representation of the variational signal waveform. The proposed waveform model can accurately generate the signal waveform at any process corner for accurate timing analysis. We generated the prosed model for gates of a 90nm industry library and validated with SPICE simulations. Our model for logic gates and variational waveforms showed very good correlation with SPICE. The maximum error across all validation experiments was close to 3%.

REFERENCES

• 1: CCS Timing White Paper, synopsys inc.
• 2: Chirayu S. Amin , Florentin Dartu , Yehea I. Ismail, Weibull Based Analytical Waveform Model, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.161, November 09-13, 2003 [doi>10.1109/ICCAD.2003.150]
• 3: Sarvesh Bhardwaj , Praveen Ghanta , Sarma Vrudhula, A framework for statistical timing analysis using non-linear delay and slew models, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233546]
• 4: E. Dartu, N. Menezes, and L. Pilegg. Performance computation for precharacterized cmos gates with rc-loads. In IEEE Transactions on CAD, vol. 15, 1996.
• 5: A. R. et al. Accurate waveform modeling using singular value decomposition with applications to timing analysis. In DAC, 2007.
• 6: Hanif Fatemi , Shahin Nazarian , Massoud Pedram, Statistical logic cell delay analysis using a current-based model, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146975]
• 7: Roger G. Ghanem , Pol D. Spanos, Stochastic finite elements: a spectral approach, Springer-Verlag New York, Inc., New York, NY, 1991
• 8: A. Goel and S. Vrudhula. Current source based standard cell model for accurate signal integrity and timing analysis. In Proceedings of the Design Automation and Test in Europe Conference (DATE), 2008.
• 9: Alexander Korshak, An Effective Current Source Cell Model for VDSM Delay Calculation, Proceedings of the 2nd International Symposium on Quality Electronic Design, p.296, March 26-28, 2001
• 10: Bao Liu, Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations, Proceedings of the 8th International Symposium on Quality Electronic Design, p.257-262, March 26-28, 2007 [doi>10.1109/ISQED.2007.84]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance, Standardization

Keywords:
process variations, statistical waveform models, timing analysis