Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques

ABSTRACT

Compared with single-issue general purpose processors (GPPs), extensible multi-issue/VLIW processors can exploit instruction-level parallelism, which are more suitable for computation intensive tasks. Moreover, they offer the ability of customizing computation accelerators for an application domain. In this paper, we present an automated methodology that customizes computation accelerators for the multi-issue/VLIW extensible processors, where several techniques are also proposed to optimize the design of an accelerator.

REFERENCES

• 1: Kubilay Atasu , Laura Pozzi , Paolo Ienne, Automatic application-specific instruction-set extensions under microarchitectural constraints, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775897]
• 2: A. Peymandoust, L. Pozzi, P. Ienne, G. De Micheli: 'Automatic Instruction Set Extension and Utilization for Embedded Processors'. In ASAP, Hague, Netherlands, June 2003, pp. 108--118
• 3: Nathan Clark , Hongtao Zhong , Scott Mahlke, Processor Acceleration Through Automated Instruction Set Customization, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.129, December 03-05, 2003
• 4: Paolo Bonzini , Laura Pozzi, Polynomial-time subgraph enumeration for automated instruction set extension, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
• 5: Xiaoyong Chen, Douglas Maskell and Yang Sun, Fast Identification of Custom Instructions for Extensible Processors, IEEE TCAD, Feb 2007
• 6: Nathan Clark , Amir Hormati , Scott Mahlke , Sami Yehia, Scalable subgraph mapping for acyclic computation accelerators, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea [doi>10.1145/1176760.1176779]
• 7: Pan Yu , Tulika Mitra, Characterizing embedded applications for instruction-set extensible processors, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996764]
• 8: Nathan T. Clark , Hongtao Zhong , Scott A. Mahlke, Automated Custom Instruction Generation for Domain-Specific Processor Acceleration, IEEE Transactions on Computers, v.54 n.10, p.1258-1270, October 2005 [doi>10.1109/TC.2005.156]
• 9: http://www.cs.tut.fi/~move/

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles

General Terms:
Algorithms, Design, Performance

Keywords:
ASIPs, VLIW, extensible processors, subgraph covering