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Multicore design is the challenge! what is the solution?
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 45th annual Design Automation Conference table of contents
Anaheim, California
PANEL SESSION: Panel table of contents
Pages 128-130  
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
Authors
Eshel Haritan  CoWare, Inc., San Jose, CA
Toshihiro Hattori  Renesas Technology Corp., Kodaira, Tokyo, Japan
Hiroyuki Yagi  STARC Yokohama, Kanagawa, Japan
Pierre Paulin  STMicroelectronics, Ottawa, Ontario, Canada
Wayne Wolf  Georgia Institute of Technology, Atlanta, GA
Achim Nohl  CoWare, Inc., Aachen, North Rhine-Westphalia, Germany
Drew Wingard  Sonics Inc., Mountain View, CA
Mike Muller  ARM Limited
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: IEEE/CASS/CANDE/CEDA
: The EDA Consortium
Publisher
ACM  New York, NY, USA
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ABSTRACT

Multi Processor SoC (MPSoC) are being designed today. MPSoC design can help achieve aggressive performance and low power targets but it creates new design challenges: How to design the interconnect fabric and memory sub-system to allow the massive data movement required in a multi processor SoC environment? How to develop, debug and verify HW and SW functionality in a MPSoC design? Is MPSoC design an inflection point that will require new design methods including ESL methodologies?


Collaborative Colleagues:
Eshel Haritan: colleagues
Toshihiro Hattori: colleagues
Hiroyuki Yagi: colleagues
Pierre Paulin: colleagues
Wayne Wolf: colleagues
Achim Nohl: colleagues
Drew Wingard: colleagues
Mike Muller: colleagues