A MIPS R2000 implementation

ABSTRACT

Thirty-four undergraduates implemented a MIPS R2000 processor for an introductory CMOS VLSI design course. This included designing a microarchitecture in Verilog, developing custom PLA generation and ad-hoc random testing tools, creating a standard cell library, schematics, layout, and PCB test board. The processor was fabricated by MOSIS on an AMI 0.5-micron process, included 160,000 transistors, and ran at 7.25 MHz.

REFERENCES

• 1: M. Horowitz, et. al., "MIPS-X: a 20-MIPS peak, 32-bit microprocessor," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 790--799, Oct. 1987.
• 2: Dominic Sweetman, See MIPS run, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1999
• 3: "Google Code hmc-mips," http://code.google.com/p/hmc-mips/
• 4: "E158 CMOS VLSI Design Spring 2007 MIPS Project," http://www4.hmc.edu:8001/Engineering/158/07/project/
• 5: A. Weiss, "Dhrystone Benchmark: History, Analysis, 'Scores,' and Recommendations White Paper," Nov. 2002, http://www.synchromeshcomputing.com/pdf/dhrystoneWhitePaper.pdf
• 6: D. Grevenstein, "Dhyrstone Benchmark Results," http://sites.inka.de/pcde/dbp/dhrystone.html

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers
          Subjects: Microprocessors

General Terms:
Design

Keywords:
MIPS, RISC