A 242mW, 10mm21080p H.264/AVC high profile encoder chip

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A 242mW, 10mm²1080p H.264/AVC high profile encoder chip

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 45th annual Design Automation Conference table of contents

Anaheim, California

SESSION: Special session: student design contest table of contents

Pages 78-83

Year of Publication: 2008

ISBN ~ ISSN:0738-100X , 978-1-60558-115-6

Authors

Yu-Kun Lin	National Chiao-Tung University, Hsinchu, Taiwan
De-Wei Li	National Chiao-Tung University, Hsinchu, Taiwan
Chia-Chun Lin	National Chiao-Tung University, Hsinchu, Taiwan
Tzu-Yun Kuo	National Chiao-Tung University, Hsinchu, Taiwan
Sian-Jin Wu	National Chiao-Tung University, Hsinchu, Taiwan
Wei-Cheng Tai	National Chiao-Tung University, Hsinchu, Taiwan
Wei-Cheng Chang	National Chiao-Tung University, Hsinchu, Taiwan
Tian-Sheuan Chang	National Chiao-Tung University, Hsinchu, Taiwan

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
: IEEE/CASS/CANDE/CEDA
: The EDA Consortium

Publisher

ACM New York, NY, USA

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ABSTRACT

A 1080p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13μm CMOS technology with an area of 10 mm² and 242mW at 145MHz. Compared to the state-of-the-art design targeted at 720p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Y. W. Huang, and et al., "A 1.3TOPS H.264/AVC singlechip encoder for HDTV applications," ISSCC Dig. Tech. Papers, vol. 1, pp. 128--588, Feb. 2005.
	2	H. C. Chang, and et al., "A 7m W~183mW Dynamic Quality-Scalable H.264 Video Encoder Chip," ISSCC Dig. Tech. Papers, pp. 128--588, Feb. 2007.
	3	T. C. Chen, and et al., "2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications," Dig. Symp. on VLSI Circuits, pp. 222--223, June 2007.
	4	C. C. Lin, Y. K. Lin, and T. S. Chang, "PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding," in proc. ICASSP, vol. 2, pp. 385--388, Apr. 2007.
	5	T. C. Chen, and et al., "Analysis and Architecture Design of an HDTV720p 30 Frames/s H.264/AVC Encoder," IEEE Trans. Circuits Syst. Video Technol., vol. 16, no.6, pp. 673--688, June 2006.
	6	Joint Video Team Reference Software JM9.0, ITU-T.