|
ABSTRACT
In this paper we present the design of a G. 729a codec in a C-based design flow. The codec is used in VoIP applications for sending speech over internet protocol. We started from the standard reference C implementation and generated several customized designs using the NISCT C-to-RTL toolset. Our final designs could run at very low clock frequencies (11 MHz for the decoder and 30 MHz for the coder) while meeting the timing requirements of the standard. We present these designs and the corresponding C-based design flow in this paper.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
|
| |
3
|
Tensilica Inc. http://www.tenisilica.com
|
| |
4
|
A Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, A. Wieferink, H. Meyr, "A Novel Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using a Machine Description Language", IEEE Transactions on Computer-Aided Design, 20(11): 1338--1354, 2001.
|
| |
5
|
Oliver Schliebusch , A. Chattopadhyay , R. Leupers , G. Ascheid , H. Meyr , Mario Steinert , Gunnar Braun , Achim Nohl, RTL Processor Synthesis for Architecture Exploration and Implementation, Proceedings of the conference on Design, automation and test in Europe, p.30156, February 16-20, 2004
|
 |
6
|
Ashok Halambi , Peter Grun , Vijay Ganesh , Asheesh Khare , Nikil Dutt , Alex Nicolau, EXPRESSION: a language for architecture exploration through compiler/simulator retargetability, Proceedings of the conference on Design, automation and test in Europe, p.100-es, January 1999, Munich, Germany
[doi> 10.1145/307418.307549]
|
| |
7
|
M. Schroeder and B. Atal, "Code-excited linear prediction (celp): High-quality speech at very low bit rates", in Proceedings IEEE International Conference on Acoustics, Speech and Signal Processing, 1984.
|
| |
8
|
ITU-T Website: http://www.itu.int/
|
| |
9
|
NISC Technology website http://www.cecs.uci.edu/~nisc/.
|
| |
10
|
A. Agrawala, T. Rauscher, Foundations of Microprogramming: "Architecture, Software, and Applications", Academic Press, 1976.
|
| |
11
|
|
| |
12
|
M. Reshadi, D. Gajski, "A Cycle-Accurate Compilation Algorithm for Custom Pipelined Datapaths", CODES+ISSS, 2005.
|
| |
13
|
B. Gorjiara, M. Reshadi, D. Gajski, "Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs", in International Conference on Computer Design (ICCD), 2006.
|
 |
14
|
|
 |
15
|
|
 |
16
|
|
| |
17
|
Robert Schreiber , Shail Aditya , Scott Mahlke , Vinod Kathail , B. Ramakrishna Rau , Darren Cronquist , Mukund Sivaraman, PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators, Journal of VLSI Signal Processing Systems, v.31 n.2, p.127-142, June 2002
[doi> 10.1023/A:1015341305426]
|
| |
18
|
N. Clark, H. Zhong, K. Fan, S. Mahlke, K. Flautner, K. Van Nieuwenhove, "OptimoDE: Programmable Accelerator Engines Through Retargetable Customization", Hot Chips, 2004.
|
| |
19
|
M. Byatt, "Data plane processing with configurable architectures", ARM white paper, 2003.
|
| |
20
|
S. Bashford, U. Bieker, B. Harking, R. Leupers, P. Marwedel, A. Neumann, D. Voggenauer, "The MIMOLA Language - Version 4.1. Technical Report." Computer Science Dpt, University of Dortmund, Sept. 1994.
|
| |
21
|
S. Weber and K. Keutzer, "Using Minimal Minterms to Represent Programmability", CODES+ISSS, 2005.
|
| |
22
|
|
 |
23
|
|
| |
24
|
|
| |
25
|
Refactoring catalog. http://www.refactoring.com/catalog/
|
| |
26
|
Pramod Chandraiah, Rainer Dömer, "Pointer Re-coding for Creating Definitive MPSoC Models", CODES+ISSS, 2007.
|
| |
27
|
Sumit Gupta, R. K. Gupta, N. D. Dutt, A. Nicolau, "SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits", Kluwer Academic Publishers, 2004.
|
| |
28
|
Silicon Integration Initiative website: http://www.si2.org/
|
|