ACM Home Page
Please provide us with feedback. Feedback
Rapid application specific floating-point unit generation with bit-alignment
Full text PdfPdf (478 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 45th annual Design Automation Conference table of contents
Anaheim, California
SESSION: Novel techniques in embedded processor design table of contents
Pages 62-67  
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
Authors
Yee Jern Chong  The University of New South Wales, Sydney, Australia
Sri Parameswaran  The University of New South Wales, Sydney, Australia
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: IEEE/CASS/CANDE/CEDA
: The EDA Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 8,   Downloads (12 Months): 53,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1391469.1391487
What is a DOI?

ABSTRACT

While ASIPs have allowed designers to create processors with custom instructions to target specific applications, floatingpoint units are still instantiated as fixed general-purpose units, which wastes area if not fully utilized. Therefore, there is a need for custom FPUs for embedded systems. The creation of a custom FPU requires the selection of a subset of the full floating-point instruction set and the implementation of this subset in hardware, such that the runtime of the application is minimized. To minimize area, it is desirable to merge the datapaths for each of the floating-point operations, so that redundant hardware is minimized. Floating-point datapaths are complex and contain components with varying bit-widths, so sharing components of different bit-widths is necessary. However, this introduces the problem of bit-alignment, which involves determining how smaller resources should be aligned within larger resources when merged. This is a problem that has been largely neglected in previous work.

Thus, this paper presents a novel algorithm for solving the bit-alignment problem, which neatly integrates into the datapath merging process. By solving this bit-alignment problem, automatic datapath merging can be made available for FPU generation. To explore the trade-offs between area and performance, a rapid design space exploration was performed to determine which FP operations should be implemented in hardware rather than emulated. Our results show that more floating-point hardware does not necessarily equate to lower run-time if the additional hardware increases delay. We found that bit-alignment reduced area by an average of 22.5% in our benchmarks, compared to an average of 14.1% without bit-alignment.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Xtensa Processor. Tensilica Inc. http://www.tensilica.com.
 
2
ARCtangent. ARC International. http://www.arc.com.
 
3
ASIP Meister. ASIP Solutions. http://www.asip-solutions.com.
 
4
5
 
6
Chia-Jeng Tseng and D. P. Siewiorek. Automated Synthesis of Data Paths in Digital Systems. In IEEE Trans. Computer-Aided Design Integr. Circuits Syst., volume 5, pages 379--395, July 1986.
 
7
 
8
 
9
 
10
 
11
N. Moreano, E. Borin, C. Souza, and G. Araujo. Efficient Datapath Merging for Partially Reconfigurable Architectures. In IEEE Trans. Computer-Aided Design Integr. Circuits Syst., volume 24, pages 969--980, July 2005.
12
 
13
K. Schoofs, G. Goossens, and HG Man. Bit-Alignment in Hardware Allocation for Multiplexed DSP Architectures. In European Conference on Design Automation, pages 289--293, Feb 1993.
 
14
 
15
M. R. Garey and D. S. Johnson. Computers and Intractability. W. H. Freeman and Company, 1979.
 
16
Cliquer. http://users.tkk.fi/~pat/cliquer.html.
 
17
SimpleScalar Tool Set. http://www.simplescalar.com.
 
18
 
19
IEEE standard for binary floating-point arithmetic, 1985.
 
20
 
21
 
22
Synopsys Tool Set. http://www.synopsys.com.
 
23
SoftFloat. http://www.jhauser.us/arithmetic/SoftFloat.html.

Collaborative Colleagues:
Yee Jern Chong: colleagues
Sri Parameswaran: colleagues