Run-time instruction set selection in a transmutable embedded processor

ABSTRACT

We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run-time. In those scenarios, current (extensible) embedded processors are less efficient since they are not run-time adaptive. We have identified the instruction set selection to be a critical step to perform at run time and hence we focus this paper on that crucial part. Our paradigm conducts as many steps as possible at compile/design time and as little as necessary at run time with the constraint to provide a sufficient flexibility to react to non-predictive application behavior efficiently. We provide an in-depth analysis of our scheme and achieve a speed-up of up to 7.19x (average: 3.63x) compared to state-of-the-art adaptive approaches (like [19]). As an application, we have employed a whole H.264 video encoder though our scheme is by principle applicable to many other embedded applications. Our results are evaluated by an implementation of the instruction set selection for our transmutable processor on an FPGA platform.

REFERENCES

• 1: Xtensa processor, Tensilica Inc. (http://www.tensilica.com)
• 2: ARCtangent processor. ARC Intl. (http://www.arc.com)
• 3: CoWare Inc, LISA Tek (http://www.coware.com)
• 4: Target Compiler (http://www.retarget.com)
• 5: ASIP Meister (http://asip-solutions.com)
• 6: Stretch processor (http://www.stretchinc.com)
• 7: CoSy compiler, ACE bv (http://www.ace.nl/compiler/cosy.html)
• 8: Jörg Henkel, Closing the SoC Design Gap, Computer, v.36 n.9, p.119-121, September 2003 [doi>10.1109/MC.2003.1231200]
• 9: Nathan Clark , Hongtao Zhong , Scott Mahlke, Processor Acceleration Through Automated Instruction Set Customization, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.129, December 03-05, 2003
• 10: Kubilay Atasu , Laura Pozzi , Paolo Ienne, Automatic application-specific instruction-set extensions under microarchitectural constraints, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775897]
• 11: Fei Sun , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha, A Scalable Application-Specific Processor Synthesis Methodology, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.283, November 09-13, 2003 [doi>10.1109/ICCAD.2003.18]
• 12: Newton Cheung , Jorg Henkel , Sri Parameswaran, Rapid Configuration and Instruction Selection for an ASIP: A Case Study, Proceedings of the conference on Design, Automation and Test in Europe, p.10802, March 03-07, 2003
• 13: Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002 [doi>10.1145/508352.508353]
• 14: Francisco Barat , Rudy Lauwereins, Reconfigurable Instruction Set Processors: A Survey, Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), p.168, June 21-23, 2000
• 15: S. Vassiliadis, D. Soudris, "Fine- and Coarse-Grain Reconfigurable Computing", Springer 2007
• 16: F. Bouwens, M. Berekovic, A. Kanstein, G. Gaydadjiev "Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array", ARC 2007, pp. 1--13
• 17: Stamatis Vassiliadis , Stephan Wong , Georgi Gaydadjiev , Koen Bertels , Georgi Kuzmanov , Elena Moscu Panainte, The MOLEN Polymorphic Processor, IEEE Transactions on Computers, v.53 n.11, p.1363-1375, November 2004 [doi>10.1109/TC.2004.104]
• 18: Roman Lysecky , Greg Stitt , Frank Vahid, Warp Processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.659-681, July 2006
• 19: Michael Dales, Managing a Reconfigurable Processor in a General Purpose Workstation Environment, Proceedings of the conference on Design, Automation and Test in Europe, p.10980, March 03-07, 2003
• 20: E. Lübbers, M. Platzner "ReconOS: An RTOS supporting Hard- and Software Threads", FPL 2007, pp. 441--446
• 21: Lars Bauer , Muhammad Shafique , Simon Kramer , Jörg Henkel, RISPP: rotating instruction set processing platform, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278678]
• 22: L. Bauer, M. Shafique, J. Henkel "Efficient Resource Utilization for an Extensible Processor through Dynamic Instruction Set Adaptation", WASP 2007, pp. 39--46
• 23: L. Bauer, M. Shafique, S. Kreutz, J. Henkel "Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set", DATE 2008, pp. 752--757
• 24: Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
• 25: S. Martello, P. Toth "Knapsack problems", Wiley 1990
• 26: Juraj Hromkovic , Waldyr M. Oliva, Algorithmics for Hard Problems, Springer-Verlag New York, Inc., Secaucus, NJ, 2002

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

General Terms:
Design, Performance

Keywords:
ASIP, extensible embedded processors, reconfigurable computing, run-time adaptation, special instruction