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Analog placement based on hierarchical module clustering
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 45th annual Design Automation Conference table of contents
Anaheim, California
SESSION: Analog performance modeling and synthesis table of contents
Pages 50-55  
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
Authors
Po-Hung Lin  National Taiwan University, Taipei, Taiwan and Springsoft, Inc., Hsinchu, Taiwan
Shyh-Chang Lin  Springsoft, Inc., Hsinchu, Taiwan
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: IEEE/CASS/CANDE/CEDA
: The EDA Consortium
Publisher
ACM  New York, NY, USA
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ABSTRACT

In analog layout design, it is very important to reduce the parasitic coupling effects and improve the circuit performance. Consequently, the most important device-level placement constraints are matching, symmetry, and proximity. However, many previous works deal with these constraints separately, and none of them mention how to handle different constraints simultaneously and hierarchically. In this paper, we first give a case study to show the needs of integrating these constraints in a hierarchical manner. Then, we present the first formulation for analog placement based on hierarchical module clustering. Our approach can handle analog placement with various constraint groups including matching, (hierarchical) symmetry, and (hierarchical) proximity groups. To our best knowledge, this is also the first work in the literature to handle floorplanning with the clustering constraint using the B*-tree based representation. Experimental results based on industrial analog designs show that our approach is very effective and efficient.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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T.-C. Chen and Y.-W. Chang, "Modern floorplanning based on B*-trees and fast simulated annealing," IEEE TCAD, vol. 25, no. 4, pp. 637--650, Apr. 2006.
 
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M. Chrzanowska-Jeske, B. Wang, and G. Greenwood, "Floorplanning with performance-based clustering," Proc. ISCAS, vol. 4, pp. 724--727, 2003.
 
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S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing," Science, vol. 220, no. 4598, pp. 671--680, May 1983.
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P.-H. Lin, H.-C. Yu, T.-H. Tsai, and S.-C. Lin, "A matching-based placement and routing system for analog design," Proc. VLSI-DAT, pp. 16--19, 2007.
 
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W.-S. Yuen and E. F.-Y. Young, "Slicing floorplan with clustering constraint," IEEE TCAD, vol. 22, no. 5, pp. 652--658, May 2003.
 
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X. Zhu, S. Nakatake, Y. Kajitani, and N. Ono, "Floorplanning consistent with partial-clustering on the sequence-pair," ICCCAS, pp. 1386--1390, 2002.


Collaborative Colleagues:
Po-Hung Lin: colleagues
Shyh-Chang Lin: colleagues