| Topology synthesis of analog circuits based on adaptively generated building blocks |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 45th annual Design Automation Conference
table of contents
Anaheim, California
SESSION: Analog performance modeling and synthesis
table of contents
Pages 44-49
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
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Authors
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Angan Das
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University of Cincinnati, Cincinnati, Ohio
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Ranga Vemuri
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University of Cincinnati, Cincinnati, Ohio
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Downloads (6 Weeks): 17, Downloads (12 Months): 69, Citation Count: 0
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ABSTRACT
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topology generation. A new kind of GA is developed, where a fraction of the offsprings in each generation is built from building blocks or cells obtained from previous generations. The cells are stored in a hierarchically arranged library that also contains information on the preferred neighborhood of each cell. The adaptively formed cell library starts only with basic elements and gradually includes functionally useful and bigger blocks, pertinent to the design. The techniques have been applied to synthesize an operational amplifier and a ring oscillator design. Results show that with reasonable computational effort, topologies have evolved that are designer understandable.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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