Enhancing timing-driven FPGA placement for pipelined netlists

ABSTRACT

FPGA application developers often use pipelining, C-slowing and retiming to improve the performance of their designs. Unfortunately, registered netlists present a fundamentally different problem to CAD tools, potentially limiting the benefit of these techniques. In this paper we discuss some of the inherent issues pipelined netlists pose to existing timing-driven placement approaches. We then present two algorithmic modifications that reduce post-routing critical path delay by an average of 40%.

REFERENCES

• 1: Ken Eguro , Scott Hauck, Armada: timing-driven pipeline-aware routing for FPGAs, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA [doi>10.1145/1117201.1117227]
• 2: Leiserson, C. and J. Saxe, "Retiming Synchronous Circuitry", Algorithmica, Vol. 6, 1991: 5--35.
• 3: Alexander Marquardt , Vaughn Betz , Jonathan Rose, Timing-driven placement for FPGAs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.203-213, February 10-11, 2000, Monterey, California, United States [doi>10.1145/329166.329208]
• 4: Larry McMurchie , Carl Ebeling, PathFinder: a negotiation-based performance-driven router for FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.111-117, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201328]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Algorithms, Design

Keywords:
FPGA, pipelined, placement, simulated annealing, timing-driven