| Sparse matrix computations on manycore GPU's |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 45th annual Design Automation Conference
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Anaheim, California
SESSION: Special session: enabling concurrency in EDA
table of contents
Pages 2-6
Year of Publication: 2008
ISBN ~ ISSN:0738-100X , 978-1-60558-115-6
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Downloads (6 Weeks): 53, Downloads (12 Months): 400, Citation Count: 1
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ABSTRACT
Modern microprocessors are becoming increasingly parallel devices, and GPUs are at the leading edge of this trend. Designing parallel algorithms for manycore chips like the GPU can present interesting challenges, particularly for computations on sparse data structures. One particularly common example is the collection of sparse matrix solvers and combinatorial graph algorithms that form the core of many physical simulation techniques. Although seemingly irregular, these operations can often be implemented with data parallel operations that map very well to massively parallel processors.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/1362622.1362674]
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