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RaceTM: detecting data races using transactional memory
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ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures table of contents
Munich, Germany
SESSION: Brief announcements table of contents
Pages 104-106  
Year of Publication: 2008
ISBN:978-1-59593-973-9
Authors
Shantanu Gupta  University of Michigan, Ann Arbor, MI, USA
Florin Sultan  NEC Laboratories America, Princeton, NJ, USA
Srihari Cadambi  NEC Laboratories America, Princeton, NJ, USA
Franjo Ivancic  NEC Laboratories America, Princeton, NJ, USA
Martin Roetteler  NEC Laboratories America, Princeton, NJ, USA
Sponsors
ACM: Association for Computing Machinery
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to more hardware concurrency. Dependable multithreaded software will have to rely on the ability to dynamically detect data races, which are non-deterministic and notoriously hard to reproduce symptoms of synchronization bugs. In this paper, we propose RaceTM, a novel approach that exploits transactional memory support to detect data races. We introduce the concept of lightweight debug transactions that exploit the conflict detection mechanisms of transactional memory systems to perform data race detection. Debug transactions differ from regular transactions in that they do not need to be rolled back, and therefore require no versioning or checkpointing support. Debug transactions do not overlap with a regular transaction, thus providing a transparent mechanism to leverage existing transactional memory support for data race detection.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. E. Ramadan, C. J. Rossbach, D. E. Porter, O. S. Hofmann, A. Bhandari, and E. Witchel. TxLinux: Using and Managing Transactional Memory in an Operating System. 2007.
 
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M. Tremblay and S. Chaudhry. A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC Processor. In Proceedings of the 2008 IEEE International multi-threaded Solid State Circuits Conference. IEEE, 2008.

Collaborative Colleagues:
Shantanu Gupta: colleagues
Florin Sultan: colleagues
Srihari Cadambi: colleagues
Franjo Ivancic: colleagues
Martin Roetteler: colleagues