Exploiting idle register classes for fast spill destination

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Exploiting idle register classes for fast spill destination

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International Conference on Supercomputing archive
Proceedings of the 22nd annual international conference on Supercomputing table of contents

Island of Kos, Greece

SESSION: Architecture 2 table of contents

Pages 319-326

Year of Publication: 2008

ISBN:978-1-60558-158-3

Authors

Fang Lu	Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Lei Wang	Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiaobing Feng	Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Zhiyuan Li	Purdue University, West Lafayette, IN, USA
Zhaoqing Zhang	Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

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ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture

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ACM New York, NY, USA

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ABSTRACT

On today's microprocessors, there often exist several different types of registers, e.g. general purpose registers and floating point registers. A given program may use one type of registers much more frequently than other types. This creates an opportunity to employ the infrequently used registers as spill destinations for the more frequently used register types. In this paper, we present a code optimization method named idle register exploitation (IRE) to exploit such opportunities. We developed a model, called the IRE model, or IREM, to determine the static performance gains of IRE versus spilling to the stack. On a microprocessor with fast data paths between different types of registers, we find that IRE method speeds up the execution of the SPECint benchmark suite from 1.7% to 10%. In contrast, on microprocessors with less efficient data transfer paths, the performance gain is limited. In some cases, performance may even suffer degradation. This result argues strongly for the adoption of fast data paths between different types of registers for the purpose of reducing register spills, which is important in view of the increased significance of memory bottlenecks on future microprocessors.

REFERENCES

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