The shared-thread multiprocessor

ABSTRACT

This paper describes initial results for an architecture called the Shared-Thread Multiprocessor (STMP). The STMP combines features of a multithreaded processor and a chip multiprocessor; specifically, it enables distinct cores on a chip multiprocessor to share thread state. This shared thread state allows the system to schedule threads from a shared pool onto individual cores, allowing for rapid movement of threads between cores.

This paper demonstrates and evaluates three benefits of this architecture:

(1) By providing more thread state storage than available in the cores themselves, the architecture enjoys the ILP benefits of many threads, but carries the in-core complexity of supporting just a few.

(2) Threads can move between cores fast enough to hide long-latency events such as memory accesses. This enables very-short-term load balancing in response to such events.

(3) The system can redistribute threads to maximize symbiotic behavior and balance load much more often than traditional operating system thread scheduling and context switching.

REFERENCES

• 1: Arvind, Data flow languages and architectures, Proceedings of the 8th annual symposium on Computer Architecture, p.1, May 12-14, 1981, Minneapolis, Minnesota, United States
• 2: K. Arvind , Rishiyur S. Nikhil, Executing a Program on the MIT Tagged-Token Dataflow Architecture, IEEE Transactions on Computers, v.39 n.3, p.300-318, March 1990 [doi>10.1109/12.48862]
• 3: J. Clabes, J. Friedrich, and M. S. et al. Design and implementation of the Power5 microprocessor. In International Solid-State Circuits Conference, 2004.
• 4: Theofanis Constantinou , Yiannakis Sazeides , Pierre Michaud , Damien Fetis , Andre Seznec, Performance implications of single thread migration on a chip multi-core, ACM SIGARCH Computer Architecture News, v.33 n.4, November 2005 [doi>10.1145/1105734.1105745]
• 5: J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, E. Chan, Y. Chan, D. Plass, S. Chu, H. Le, L. Clark, J. Ripley, S. Taylor, J. Dilullo, and M. Lanzerotti. Design of the Power6 microprocessor. In International Solid-State Circuits Conference, Feb. 2007.
• 6: Tim Johnson , Umesh Nawathe, An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2), Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA [doi>10.1145/1231996.1232000]
• 7: R. H. Katz , S. J. Eggers , D. A. Wood , C. L. Perkins , R. G. Sheldon, Implementing a cache consistency protocol, Proceedings of the 12th annual international symposium on Computer architecture, p.276-283, June 17-19, 1985, Boston, Massachusetts, United States
• 8: Poonacha Kongetira , Kathirgamar Aingaran , Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, v.25 n.2, p.21-29, March 2005 [doi>10.1109/MM.2005.35]
• 9: David Koufaty , Deborah T. Marr, Hyperthreading Technology in the Netburst Microarchitecture, IEEE Micro, v.23 n.2, p.56-65, March 2003 [doi>10.1109/MM.2003.1196115]
• 10: S. Parekh, S. Eggers, and H. Levy. Thread-sensitive scheduling for SMT processors. Technical report, University of Washington, 2000.
• 11: Allan Snavely , Dean M. Tullsen, Symbiotic jobscheduling for a simultaneous multithreaded processor, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.234-244, November 2000, Cambridge, Massachusetts, United States
• 12: Lawrence Spracklen , Santosh G. Abraham, Chip Multithreading: Opportunities and Challenges, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.248-252, February 12-16, 2005 [doi>10.1109/HPCA.2005.10]
• 13: K. Stavrou, C. Kyriacou, P. Evripidou, and P. Trancoso. Chip multiprocessor based on data-driven multithreading model. In International Journal of High Performance System Architecture, 2007.
• 14: Josep Torrellas , Andrew Tucker , Anoop Gupta, Evaluating the performance of cache-affinity scheduling in shared-memory multiprocessors, Journal of Parallel and Distributed Computing, v.24 n.2, p.139-151, Feb. 1, 1995 [doi>10.1006/jpdc.1995.1014]
• 15: D. Tullsen. Simulation and modeling of a simultaneous multithreading processor. In 22nd Annual Computer Measurement Group Conference, Dec. 1996.
• 16: Dean M. Tullsen , Jeffery A. Brown, Handling long-latency loads in a simultaneous multithreading processor, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
• 17: Dean M. Tullsen , Susan J. Eggers , Joel S. Emer , Henry M. Levy , Jack L. Lo , Rebecca L. Stamm, Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, Proceedings of the 23rd annual international symposium on Computer architecture, p.191-202, May 22-24, 1996, Philadelphia, Pennsylvania, United States
• 18: Dean M. Tullsen , Susan J. Eggers , Henry M. Levy, Simultaneous multithreading: maximizing on-chip parallelism, Proceedings of the 22nd annual international symposium on Computer architecture, p.392-403, June 22-24, 1995, S. Margherita Ligure, Italy
• 19: Eric Tune , Rakesh Kumar , Dean M. Tullsen , Brad Calder, Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.183-194, December 04-08, 2004, Portland, Oregon [doi>10.1109/MICRO.2004.8]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Multiple-instruction-stream, multiple-data-stream processors (MIMD)

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes

General Terms:
Design, Performance

Keywords:
chip multiprocessors, simultaneous multithreading