An approach for adaptive DRAM temperature and power management

ABSTRACT

With rising capacities and higher accessing frequencies, high-performance DRAMs are providing increasing memory access bandwidth to the processors. However, the increasing DRAM performance comes with the price of higher power consumption and temperature in DRAM chips. Traditional low power approaches for DRAM systems focus on utilizing low power modes, which is not always suitable for high performance systems. Existing DRAM temperature management techniques, on the other hand, utilize generic temperature management methods inherited from those applied on processor cores. These methods reduce DRAM temperature by controlling the number of DRAM accesses, similar to throttling the processor core, which incurs significant performance penalty. In this paper, we propose a customized low power technique for high performance DRAM systems, namely the Page Hit Aware Write Buffer (PHA-WB). The PHA-WB improves DRAM page hit rate by buffering write operations that may incur page misses. This approach reduces DRAM system power consumption and temperature without any performance penalty. Our proposed Throughput-Aware PHA-WB (TAP) dynamically configures the write buffer for different applications and workloads, thus achieves the best trade off between DRAM power reduction and buffer power overhead. Our experiments show that a system with TAP could reduce the total DRAM power consumption by up to 18.36% (8.64% on average). The steady-state temperature can be reduced by as much as 5.10°C and by 1.93°C on average across eight representative workloads.

REFERENCES

• 1: Nathan L. Binkert , Ronald G. Dreslinski , Lisa R. Hsu , Kevin T. Lim , Ali G. Saidi , Steven K. Reinhardt, The M5 Simulator: Modeling Networked Systems, IEEE Micro, v.26 n.4, p.52-60, July 2006 [doi>10.1109/MM.2006.82]
• 2: Victor Delaluz , Mahmut Kandemir , N. Vijaykrishnan , Anand Sivasubramaniam , Mary Jane Irwin, Hardware and Software Techniques for Controlling DRAM Power Modes, IEEE Transactions on Computers, v.50 n.11, p.1154-1173, November 2001 [doi>10.1109/12.966492]
• 3: Xiaobo Fan , Carla Ellis , Alvin Lebeck, Memory controller policies for DRAM power management, Proceedings of the 2001 international symposium on Low power electronics and design, p.129-134, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383118]
• 4: Iyer, J., C.L. Hall, J. Shi, and Y. Huang, System Memory Power and Thermal Management in Platforms Built on Intel® Centrino® Duo Mobile Technology. Intel Technology Journal, 2006.
• 5: JEDEC, FBDIMM Specification: DDR2 SDRAM Fully Buffered DIMM (FBDIMM) Design Specification http://www.jedec.org/download/search/JESD2051.pdf.
• 6: JEDEC, FBDIMM: Advanced Memory Buffer (AMB) http://www.jedec.org/download/search/JESD82-20.pdf.
• 7: Alvin R. Lebeck , Xiaobo Fan , Heng Zeng , Carla Ellis, Power aware page allocation, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.105-116, November 2000, Cambridge, Massachusetts, United States
• 8: Lee, K.-B., T.-C. Lin, and C.-W. Jen, An efficient quality-aware memory controller for multimedia platform SoC. IEEE Transactions on Circuits and Systems for Video Technology,, 2005. 15(5).
• 9: Jiang Lin , Hongzhong Zheng , Zhichun Zhu , Howard David , Zhao Zhang, Thermal modeling and management of DRAM memory systems, Proceedings of the 34th annual international symposium on Computer architecture, June 09-13, 2007, San Diego, California, USA
• 10: Lin, J., H. Zheng, Z. Zhu, Z. Zhang, and H. David, DRAM-level prefetching for fully-buffered DIMM: design, performance and power saving, in ISPASS'07. 2007.
• 11: Micron, Calculating Memory System Power for DDR2.
• 12: Micron, DDR2 SDRAM FBDIMM http://download.micron.com/pdf/datasheets/modules/ddr2/HTF18C128_256x72FD.pdf.
• 13: Micron, DDR2 SDRAM http://download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf.
• 14: Micron, System Power Calculator, http://www.micron.com/support/designsupport/tools/powercalc/powercalc.aspx.
• 15: Rambus, RDRAM, in www.rambus.com.
• 16: Scott Rixner, Memory Controller Optimizations for Web Servers, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.355-366, December 04-08, 2004, Portland, Oregon [doi>10.1109/MICRO.2004.22]
• 17: Shivakumar, P. and N.P. Jouppi, CACTI 3.0: An Integrated Cache Timing, Power, and Area Model WRL Research Report.
• 18: www.spec.org, Standard Performance Evaluation Corporation. SPEC CPU2000 .

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Primary memory

General Terms:
Design, Management, Performance

Keywords:
DRAM, power, temperature