A freespace crossbar for multi-core processors

ABSTRACT

A new package-level interconnect is described that adapts carbon nanoemissive display technology to create an inexpensive package-level freespace crossbar with single-cycle source-to-target latency. Interconnections are made using filamentary electron beams as the data transmission medium. The beams are electrostatically steered, enabling very large, low latency inter-chip crossbar networks. The crossbar and associated package are built entirely from existing technology. This paper describes the operation of the crossbar and presents a conceptual design for a processor that uses the crossbar.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

General Terms:
Design

Keywords:
freespace crossbar, interconnect