| Software thermal management of dram memory for multicore systems |
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Joint International Conference on Measurement and Modeling of Computer Systems
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Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
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Annapolis, MD, USA
Pages: 337-348
Year of Publication: 2008
ISBN:978-1-60558-005-0
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Authors
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Jiang Lin
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Iowa State University, Ames, IA, USA
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Hongzhong Zheng
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University of Illinois at Chicago, Chicago, IL, USA
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Zhichun Zhu
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University of Illinois at Chicago, Chicago, IL, USA
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Eugene Gorbatov
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Intel Corp., Hillsboro, OR, USA
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Howard David
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Intel Corp., Hillsboro, IL, USA
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Zhao Zhang
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Iowa State University, Ames, IA, USA
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Downloads (6 Weeks): 27, Downloads (12 Months): 139, Citation Count: 2
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ABSTRACT
Thermal management of DRAM memory has become a critical issue for server systems. We have done, to our best knowledge, the first study of software thermal management for memory subsystem on real machines. Two recently proposed DTM (Dynamic Thermal Management) policies have been improved and implemented in Linux OS and evaluated on two multicore servers, a Dell PowerEdge 1950 server and a customized Intel SR1500AL server testbed. The experimental results first confirm that a system-level memory DTM policy may significantly improve system performance and power efficiency, compared with existing memory bandwidth throttling scheme. A policy called DTM-ACG (Adaptive Core Gating) shows performance improvement comparable to that reported previously. The average performance improvements are 13.3% and 7.2% on the PowerEdge 1950 and the SR1500AL (vs. 16.3% from the previous simulation-based study), respectively. We also have surprising findings that reveal the weakness of the previous study: the CPU heat dissipation and its impact on DRAM memories, which were ignored, are significant factors. We have observed that the second policy, called DTM-CDVFS (Coordinated Dynamic Voltage and Frequency Scaling), has much better performance than previously reported for this reason. The average improvements are 10.8% and 15.3% on the two machines (vs. 3.4% from the previous study), respectively. It also significantly reduces the processor power by 15.5% and energy by 22.7% on average.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 2
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Hongzhong Zheng , Jiang Lin , Zhao Zhang , Eugene Gorbatov , Howard David , Zhichun Zhu, Mini-rank: Adaptive DRAM architecture for improving memory power efficiency, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.210-221, November 08-12, 2008
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