Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations

ABSTRACT

Variations in the semiconductor fabrication process results in differences in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. Field-Programmable Gate Arrays may be able to compensate for within-die delay variability, by judicious use of reconfigurability. This article presents two strategies for compensating within-die stochastic delay variability by using reconfiguration: reconfiguring the entire FPGA, and relocating subcircuits within an FPGA. Analytical models for the theoretical bounds on the achievable gains are derived for both strategies and compared to models for worst-case design as well as statistical static timing analysis (SSTA). All models are validated by comparison to circuit-level Monte Carlo simulations. It is demonstrated that significant improvements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.

REFERENCES

• 1: Miron Abramovici , Charles E. Stroud, BIST-Based Delay-Fault Testing in FPGAs, Journal of Electronic Testing: Theory and Applications, v.19 n.5, p.549-558, October 2003 [doi>10.1023/A:1025126030727]
• 2: Asenov, A., Kaya, S., and Brown, A. R. 2003. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE Trans. Electr. Devices 50, 5, 1254--1260.
• 3: Asenov, A., Kaya, S., and Davies, J. H. 2002. Intrinsic threshold voltage fluctuationsin decananometer MOSFETs due to local oxide thickness variations. IEEE Trans. Electr. Devices 49, 6, 112--119.
• 4: Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997
• 5: Cao, Y., Gupta, P., Kahng, A. B., Sylvester, D., and Yang, J. 2002. Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI. In Proceedings of the IEEE International ASIC/SOC Conference.
• 6: Cattell, R. B. 1966. The scree test for the number of factors. Multivariate Behav. Resear. 1, 245--276.
• 7: Hongliang Chang , Vladimir Zolotov , Sambasivan Narayan , Chandu Visweswariah, Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065604]
• 8: Patrick Girard , Olivier Héron , Serge Pravossoudovitch , Michel Renovell, High Quality TPG for Delay Faults in Look-Up Tables of FPGAs, Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications, p.83, January 28-30, 2004
• 9: Ian G. Harris , Premachandran R. Menon , Russell Tessier, BIST-based delay path testing in FPGA architectures, Proceedings of the IEEE International Test Conference 2001, p.932-938, October 30-November 01, 2001
• 10: Katsuki, K., Kotani, M., Kobayashi, K., and Onodera, H. 2005. A yield and speed enhancement scheme under within-die variations on 90nm LUT array. In Proceedings of the IEEE Custom Integrated Circuits Conference.
• 11: Kazuya Katsuki , Manabu Kotani , Kazutoshi Kobayashi , Hidetoshi Onodera, Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan [doi>10.1145/1118299.1118331]
• 12: Kee Sup Kim , Subhasish Mitra , Paul G. Ryan, Delay Defect Characteristics and Testing Strategies, IEEE Design & Test, v.20 n.5, p.8-16, September 2003 [doi>10.1109/MDT.2003.1232251]
• 13: Kraśniewski, A. 2003. Evaluation of testability of path delay faults for user-configured programmable devices. In Proceedings of the Field-Programmable Logic and Applications. IEEE.
• 14: Li, X.-Y., Wang, F., La, T., and Ling, Z.-M. 2004. FPGA as process monitor--an effective method to characterize poly gate CD variation and its impact on product performance and yield. IEEE Trans. Semicond. Manuf. 17, 3, 267--272.
• 15: Lin, Y., Hutton, M., and He, L. 2006. Placement and timing for FPGAs considering variations. In Proceedings of the Field-Programmable Logic and Applications. IEEE.
• 16: Yohei Matsumoto , Masakazu Hioki , Takashi Kawanami , Toshiyuki Tsutsumi , Tadashi Nakagawa , Toshihiro Sekigawa , Hanpei Koike, Performance and yield enhancement of FPGAs with within-die variation using multiple configurations, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA [doi>10.1145/1216919.1216948]
• 17: Georges Nabaa , Navid Azizi , Farid N. Najm, An adaptive FPGA architecture with process variation compensation and reduced leakage, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1147069]
• 18: Sani R. Nassif, Design for Variability in DSM Technologies, Proceedings of the 1st International Symposium on Quality of Electronic Design, p.451, March 20-22, 2000
• 19: Sedcole, P., Blodget, B., Becker, T., Anderson, J., and Lysaght, P. 2006. Modular dynamic reconfiguration in Virtex FPGAs. IEE Proc. Comput. Digital Techniq. 153, 3, 157--164.
• 20: Sedcole, P. and Cheung, P. Y. K. 2006. Within-die delay variability in 90nm FPGAs and beyond. In Proceedings of the IEEE International Conference on Field Programmable Technology.
• 21: Pete Sedcole , Peter Y. K. Cheung, Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA [doi>10.1145/1216919.1216949]
• 22: Chandu Visweswariah, Death, taxes and failing chips, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775921]
• 23: C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]
• 24: Ho-Yan Wong , Lerong Cheng , Yan Lin , Lei He, FPGA device and architecture evaluation considering process variations, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.19-24, November 06-10, 2005, San Jose, CA
• 25: Zhao, W., Liu, F., Agarwal, K., Acharyya, D., Nassif, S., Nowka, K., and Cao, Y. 2007. Rigorous extraction of process variations for 65nm CMOS design. In Proceedings of the European Solid-State Circuits Conference.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Logic arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

General Terms:
Theory

Keywords:
Delay, FPGA, modeling, process variation, reconfiguration, statistical theory, within-die variability, yield