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Software engineering for multicore systems: an experience report
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International Conference on Software Engineering archive
Proceedings of the 1st international workshop on Multicore software engineering table of contents
Leipzig, Germany
SESSION: Applications and experience reports table of contents
Pages: 53-60  
Year of Publication: 2008
ISBN:978-1-60558-031-9
Authors
Victor Pankratius  University of Karlsruhe, Karlsruhe, Germany
Christoph Schaefer  University of Karlsruhe, Karlsruhe, Germany
Ali Jannesari  University of Karlsruhe, Karlsruhe, Germany
Walter F. Tichy  University of Karlsruhe, Karlsruhe, Germany
Sponsors
SIGSOFT: ACM Special Interest Group on Software Engineering
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

The emergence of inexpensive parallel computers powered by multicore chips combined with stagnating clock rates raises new challenges for software engineering. As future performance improvements will not come "for free" from increased clock rates, performance critical applications will need to be parallelized. However, little is known about the engineering principles for parallel general-purpose applications.

This paper presents an experience report with four diverse case studies on multicore software development for general-purpose applications. They were programmed in different languages and benchmarked on several multicore computers. Empirical findings include: 1) Multicore computers deliver: Real speedups are achievable, albeit with significant programming effort and speedups that are typically lower than the number of cores employed; 2) Massive refactoring of sequential programs is required, sometimes at several levels. Special tools for parallelization refactorings appear to be an important area of research; 3) Autotuning is indispensable, as manually tuning thread assignment, number of pipeline stages, size of data partitions and other parameters is difficult and error prone; 4) Architectures that encompass several parallel components are poorly understood. Tuneable architectural patterns with parallelism at several levels need to be discovered.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Victor Pankratius: colleagues
Christoph Schaefer: colleagues
Ali Jannesari: colleagues
Walter F. Tichy: colleagues