Implementing the scale vector-thread processor

ABSTRACT

The Scale vector-thread processor is a complexity-effective solution for embedded computing which flexibly supports both vector and highly multithreaded processing. The 7.1-million transistor chip has 16 decoupled execution clusters, vector load and store units, and a nonblocking 32KB cache. An automated and iterative design and verification flow enabled a performance-, power-, and area-efficient implementation with two person-years of development effort. Scale has a core area of 16.6 mm² in 180 nm technology, and it consumes 400 mW--1.1 W while running at 260 MHz.

REFERENCES

• 1: Batten, C., Krashinsky, R., and Asanovic, K. 2007. Scale control processor test-chip. Tech. Rep. MIT-CSAIL-TR-2007-003, CSAIL Technical Reports, Massachusetts Institute of Technology.
• 2: Christopher Batten , Ronny Krashinsky , Steve Gerding , Krste Asanovic, Cache Refill/Access Decoupling for Vector Machines, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.331-342, December 04-08, 2004, Portland, Oregon [doi>10.1109/MICRO.2004.9]
• 3: David Chinnery , Kurt Keutzer, Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design, Springer-Verlag New York, Inc., Secaucus, NJ, 2005
• 4: Flachs, B., Asano, S., Dhong, S. H., Hofstee, H. P., Gervais, G., Kim, R., Le, T., Liu, P., Leenstra, J., Liberty, J., Michael, B., Oh, H.-J., Mueller, S. M., Takahashi, O., Hatakeyama, A., Watanabe, Y., Yano, N., Brokenshire, D. A., Peyravian, M., To, V., and Iwata, E. 2006. The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid-State Circ. 41, 1 (Jan.), 63--70.
• 5: Mark Hampton , Krste Asanovic, Compiling for vector-thread architectures, Proceedings of the sixth annual IEEE/ACM international symposium on Code generation and optimization, April 05-09, 2008, Boston, MA, USA [doi>10.1145/1356058.1356085]
• 6: Krashinsky, R. 2007. Vector-Thread architecture and implementation. Ph.D. thesis, Massachusetts Institute of Technology, Cambridge, MA.
• 7: Ronny Krashinsky , Christopher Batten , Mark Hampton , Steve Gerding , Brian Pharris , Jared Casper , Krste Asanovic, The Vector-Thread Architecture, Proceedings of the 31st annual international symposium on Computer architecture, p.52, June 19-23, 2004, München, Germany
• 8: Karthikeyan Sankaralingam , Ramadass Nagarajan , Robert McDonald , Rajagopalan Desikan , Saurabh Drolia , M. S. Govindan , Paul Gratz , Divya Gulati , Heather Hanson , Changkyu Kim , Haiming Liu , Nitya Ranganathan , Simha Sethumadhavan , Sadia Sharif , Premkishore Shivakumar , Stephen W. Keckler , Doug Burger, Distributed Microarchitectural Protocols in the TRIPS Prototype Processor, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.480-491, December 09-13, 2006 [doi>10.1109/MICRO.2006.19]
• 9: Taylor, M. B., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, H., Johnson, P., Lee, W., Saraf, A., Shnidman, N., Strumpen, V., Amarasinghe, S., and Agarwal, A. 2003. A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network. In Proceedings of the International Solid State Circuits Conference (ISSCC).
• 10: Turpin, M. 2003. The dangers of living with an x (bugs hidden in your Verilog). In Synopsys Users Group Meeting.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers
          Subjects: Microprocessors

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Multiple-instruction-stream, multiple-data-stream processors (MIMD); Array and vector processors; Single-instruction-stream, multiple-data-stream processors (SIMD)

General Terms:
Design, Verification

Keywords:
Vector processors, hybrid C++/Verilog simulation, iterative VLSI design flow, multithreaded processors, procedural datapath pre-placement, vector-thread processors