| Improving single-thread performance with fine-grain state maintenance |
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Conference On Computing Frontiers
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Proceedings of the 5th conference on Computing frontiers
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Ischia, Italy
SESSION: Innovative microarchitecture II
table of contents
Pages 251-260
Year of Publication: 2008
ISBN:978-1-60558-077-7
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Authors
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Peng Zhou
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Michigan Technological University, Houghton, MI, USA
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Soner Õnder
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Michigan Technological University, Houghton, MI, USA
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Downloads (6 Weeks): 7, Downloads (12 Months): 41, Citation Count: 0
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ABSTRACT
We show that a multi-threaded processor that is aware of the processor state in a fine-grain manner can improve single-thread performance significantly by assigning the task of maintaining the correct processor state to an independent thread. We develop fine-grain state maintenance techniques that can be applied in multi-threaded environments and present a fine-grain state application of runahead execution where the data values dependent on a missed load are treated as damaged values. These values are verified and recovered as necessary by an independent thread. We evaluate an SMT-like fine grain state processor and show that it obtains an average of 38.9% and up to 160.0% better performance than coarse-grain baseline processors on the SPEC CFP2000 benchmark suite.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel.The microarchitecture of the pentium 4 processor.In Intel Technology Journal, February 2001
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7
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8
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Mike Johnson.Superscalar Microprocessor Design.Prentice Hall, 1991.
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9
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Tejas Karkhanis and J. E. Smith. A day in the life of a data cache miss.In Workshop on Memory Performance Issues, Anchorage, AK, May 2002.
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10
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12
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Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt.Runahead execution: An effective alternative to large instruction windows.IEEE Micro, 23(6):20--25, 2003.
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Smruti R. Sarangi , Wei Liu, Josep Torrellas , Yuanyuan Zhou, ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.257-270, November 12-16, 2005, Barcelona, Spain
[doi> 10.1109/MICRO.2005.28]
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Srikanth T. Srinivasan , Ravi Rajwar , Haitham Akkary , Amit Gandhi , Mike Upton, Continual flow pipelines, Proceedings of the 11th international conference on Architectural support for programming languages and operating systems, October 07-13, 2004, Boston, MA, USA
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