Comparison of redundant architectures for two-step ADCs

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Comparison of redundant architectures for two-step ADCs

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Great Lakes Symposium on VLSI archive
Proceedings of the 18th ACM Great Lakes symposium on VLSI table of contents

Orlando, Florida, USA

SESSION: Session 6B: ADC and LDPC table of contents

Pages: 445-450

Year of Publication: 2008

ISBN:978-1-59593-999-9

Authors

Gian Nicola Angotzi	University of Cagliari, Cagliari, Italy
Massimo Barbaro	University of Cagliari, Cagliari, Italy
Paul G.A. Jespers	Université Catholique de Louvain, Louvain la Neuve, Belgium

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

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ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 21, Citation Count: 0

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ABSTRACT

Redundancy in the output code, as instrument to reduce the impact of non-idealities in different architectures of two-step A to D converters, is investigated. A circuit model capable of providing an estimate of the required sizes for passive components for a given accuracy was developed. Such model represents an useful design tool, providing a way to calculate important figures of merit (area, power, ENOB, SNR, large-signal behavior) of the different ADCs. System-level simulation results are provided and discussed.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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