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An analytical model for the upper bound on temperature differences on a chip
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Great Lakes Symposium on VLSI archive
Proceedings of the 18th ACM Great Lakes symposium on VLSI table of contents
Orlando, Florida, USA
SESSION: Session 6A: Low Power Architecture table of contents
Pages 417-422  
Year of Publication: 2008
ISBN:978-1-59593-999-9
Authors
Shervin Sharifi  University of California, San Diego, La Jolla, CA, USA
Tajana Simunic Rosing  University of California, San Diego, La Jolla, CA, USA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be used in many applications, such as estimation of maximum temperature variations on the die and estimating the maximum placement error in temperature sensor placement algorithms. The model also identifies the conditions under which these maximum temperature variations might happen, which is very helpful for generating test data for thermal stress tests and for augmenting different benchmarks. Experiments show that maximum temperature differences can be underestimated as much as 9°C. Based on this model, a temperature sensor placement algorithm is also proposed which is able to guaranty a maximum temperature error due to placement of the sensor. The ability of the proposed model to estimate point to point maximum temperature difference can improve the efficiency and accuracy of the sensor placement technique so that we can reduce the number of thermal sensors needed by about 16% on average.


REFERENCES

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Collaborative Colleagues:
Shervin Sharifi: colleagues
Tajana Simunic Rosing: colleagues