Simultaneous optimization of memory configuration and code allocation for low power embedded systems

ABSTRACT

This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ²ratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area overhead. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.0 General

General Terms:
Experimentation

Keywords:
code allocation, low power design, on-chip memory