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Fast bus waveform estimation at the presence of coupling noise
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Great Lakes Symposium on VLSI archive
Proceedings of the 18th ACM Great Lakes symposium on VLSI table of contents
Orlando, Florida, USA
POSTER SESSION: Poster session 2 table of contents
Pages 339-342  
Year of Publication: 2008
ISBN:978-1-59593-999-9
Authors
Jingye Xu  University of Illinois at Chicago, Chicago, IL, USA
Pervez Khaled  University of Illinois at Chicago, Chicago, IL, USA
Masud H. Chowdhury  University of Illinois at Chicago, Chicago, IL, USA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

With the technology scaling and shrinking feature sizes, coupling noise has become one of the most critical concerns in today's interconnect-centric design, especially for long global buses. A very common consequence of coupling is that the output signal waveform becomes non-monotonic. Traditionally, only through circuit simulation can the output waveform can be precisely acquired. However, this method suffers from low efficiency especially for today's super scale circuits. This paper proposes a fast algorithm to accurately estimate the output waveform for buses at the presence of coupling noise. Experimental results show that only a little more than 2% mean error is induced while, on average, the running time of the proposed algorithm is 23 times faster than HSPICE simulation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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M. Ghoneima, Yehea Ismail, "Accurate Decoupling of Capacitively Coupled Buses" International Symposium on Circuit and Systems(ISCAS), 2006.
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P. R. O?Brien and T. L. Savarino, "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation," Proceedings of IEEE International Conference on Computer-Aided Design, November 1989
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J. Qian, S. Pullela, and L. Pillage, "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates" IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol.13, Dec.1994, pp.1526--1535
 
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Collaborative Colleagues:
Jingye Xu: colleagues
Pervez Khaled: colleagues
Masud H. Chowdhury: colleagues