Design of defect tolerant tile-based QCA circuits

ABSTRACT

In this paper, a novel CAD-based approach is presented for defect tolerance of QCA circuits. This approach is based on using QCA tiles and provides defect tolerance at circuit level with, in most cases, no area overhead. A ranking methodology is introduced to determine the tile configurations and logic functions that are optimal for logic synthesis of QCA circuits. Simulations on benchmark circuits show that the proposed methodology provides significant improvements in defect tolerance compared with QCA gate-based designs.

REFERENCES

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INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Fault tolerance

General Terms:
Design, Reliability

Keywords:
missing cell, qca, simulation