Optimal sleep transistor synthesis under timing and area constraints

ABSTRACT

Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is the use of sleep transistors as power-gating elements to cut-off sub-threshold leakage current in circuits when they are in stand-by mode. Although sleep transistor insertion is very effective in cutting-off leakage, it also incurs timing, area and routing overhead. Since most of the sleep transistor insertion methodologies do post layout insertion, care should be taken such that there is minimal perturbation of the original layout. Over design of sleep transistors cells and sub-optimal sleep transistor placement must be avoided to achieve final design closure. Since the sleep transistor area plays an important and prominent role in this aspect, it necessitates for optimal sleep transistor sizing and synthesis technique under area constraints. In this paper, we first provide a methodology for optimal sleep transistor synthesis under given area constraints. We then apply our technique to the general timing and area constraint driven row-based power-gating methodology proposed in [13] and show how optimal low leakage designs with constraints on timing and area can be designed.

REFERENCES

• 1: James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277180]
• 2: M.Anis, S.Areibi, M.Elmasry, "Design and optimization of multithreshold CMOS (MTCMOS) circuits", IEEE Transactions on Computer--Aided Design of Integrated Circuits and Systems, Vol. 22, No. 10, pp. 1324--1342, October 2003.
• 3: Changbo Long , Lei He, Distributed sleep transistor network for power reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.937-946, September 2004 [doi>10.1109/TVLSI.2004.832939]
• 4: Anand Ramalingam , Bin Zhang , Anirudh Devgan , David Z. Pan, Sleep transistor sizing using timing criticality and temporal currents, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120832]
• 5: Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
• 6: W.Wang, M.Anis, S.Areibi, "Fast techniques for standby leakage reduction in MTCMOS circuits," SOCC-04: IEEE System on a Chip Conference, pp. 21--24, 2004.
• 7: Tsuang-Wei Chang , Ting-Ting Hwang , Sheng-Yu Hsu, Functionality directed clustering for low power MTCMOS design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1121056]
• 8: Pietro Babighian , Luca Benini , Alberto Macii , Enrico Macii, Post-layout leakage power minimization based on distributed sleep transistor insertion, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013275]
• 9: A. Sathanur , A. Calimera , L. Benini , A. Macii , E. Macii , M. Poncino, Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
• 10: Andrea Calimera , Antonio Pullini , Ashoka Visweswara Sathanur , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology, Proceedings of the 17th ACM Great Lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy [doi>10.1145/1228784.1228903]
• 11: Pietro Babighian , Luca Benini , Alberto Macii , Enrico Macii, Enabling fine-grain leakage management by voltage anchor insertion, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
• 12: Hyo-Sig Won , Kyo-Sun Kim , Kwang-Ok Jeong , Ki-Tae Park , Kyu-Myung Choi , Jeong-Taek Kong, An MTCMOS design methodology and its application to mobile computing, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871536]
• 13: Ashoka Sathanur , Antonio Pullini , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Timing-driven row-based power gating, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA [doi>10.1145/1283780.1283803]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
clustering, leakage power, power-gating, row-based, sleep transistor, standard cell