A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection

ABSTRACT

We propose an algorithm for sizing analog circuits using parasitic aware circuit matrix models. A novel scheme of separating schematic and parasitic models is proposed. As layout details are not abstracted in the circuit performance, the developed models can be used for different module geometries. Regression models developed make parasitic estimation much faster than a layout inclusive approach. The proposed approach is successfully used for dynamic module geometry selection during synthesis. Experiments conducted on operational amplifier and filter topologies demonstrate the accuracy of our proposed approach. For both circuits, results are within a mean error of 1 percent compared to an exact layout and spice approach.

REFERENCES

• 1: P. Vancorenland , G. Van der Plas , M. Steyaert , G. Gielen , W. Sansen, A layout-aware synthesis methodology for RF circuits, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 2: Mohamed Dessouky , Marie-Minerve Louërat , Jacky Porte, Layout-oriented synthesis of high performance analog circuits, Proceedings of the conference on Design, automation and test in Europe, p.53-57, March 27-30, 2000, Paris, France [doi>10.1145/343647.343698]
• 3: Anuradha Agarwal , Hemanth Sampath , Veena Yelamanchili , Ranga Vemuri, Fast and accurate parasitic capacitance models for layout-aware, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996610]
• 4: Gang Zhang , Aykut Dengi , Ronald A. Rohrer , Rob A. Rutenbar , L. Richard Carley, A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996612]
• 5: Almitra Pradhan , Ranga Vemuri, On the Use of Hash Tables for Efficient Analog Circuit Synthesis, Proceedings of the 21st International Conference on VLSI Design, p.647-652, January 04-08, 2008 [doi>10.1109/VLSI.2008.35]
• 6: R. Castro-Lopez, F. Fernandez, and A. Rodriguez-Vazquez, "Geometrically-constrained, parasitic aware synthesis of analog ICs," in Proc. of the SPIE, 2005, pp. 673--684.
• 7: H. Sampath and R. Vemuri, "MSL a high level language for parameterized analog and mixed signal layout generators," in Proc of the 12th IFIP VLSI Conf., 2003, pp. 416--421.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms

Keywords:
layout-aware, matrix-models, sizing