A low leakage 9t sram cell for ultra-low power operation

ABSTRACT

This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it is shown that the 9T cell achieves improvements in power dissipation, performance and stability compared with previous designs (that require 10T and 8T) for low-power operation. The 9T scheme is amenable to small feature sizes as encountered in the deep sub-micron/nano ranges of CMOS technology.

REFERENCES

• 1: Nam Sung Kim , Krisztian Flautner , David Blaauw , Trevor Mudge, Circuit and microarchitectural techniques for reducing cache leakage power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.167-184, February 2004 [doi>10.1109/TVLSL.2003.821550]
• 2: L.Chang, et al. "Stable SRAM Cell Design for the 32 nm Node and Beyond", VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on, 14-16 June 2005 Page(s):128--129
• 3: B.H. Calhoun and A.P. Chandrakasan, "A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation", in Solid-State Circuits, IEEE Journal of, Volume 42, Issue 3, March 2007 Page(s):680--688
• 4: T.-H. Kim, J. Liu, J. Keane, C.H. Kim, "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme", in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, 11-15 Feb. 2007, Page(s): 330--336

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

General Terms:
Design, Performance

Keywords:
leakage power, low power, nanotechnology, sram cell, static noise margin