A high-speed radix-4 multiplexer-based array multiplier

ABSTRACT

This paper presents a new radix-4 multiplexer-based array multiplier, based on a multiplication scheme shown in a previous work, where 4-to-1 multiplexers are used for the computation of partial products. In the proposed design, the rows of the array are reduced to the half, compared to the initial multiplexer-based scheme, as two bits from both operands are processed at each step. The proposed scheme is compared to the Modified-Booth array multiplier and to the initial multiplexer-based array scheme. The compared designs are coded in VHDL and synthesized using the TSMC 0.13¼m technology library. The synthesis results of critical time and area show 11-22% improvement in critical time delay compared to the Modified-Booth array, in the expense of an area overhead of 3.8-16%. Compared to the initial multiplexer-based scheme, there is a significant improvement in terms of area and critical time.

REFERENCES

• 1: Y. Oowaki et al., "A Sub-10-ns 16x16 Multiplier Using 0.6-nm CMOS Technology", IEEE Journal of Solid--State Circuits, vol. 22, no. 5, October 1987.
• 2: R. Sharma et al., "A 6.75-ns 16x16-bit Multiplier in Single-Level-Metal CMOS Technology", IEEE Journal of Solid State Circuits, vol. 24, no. 4, August 1989.
• 3: C. Wallace, "A suggestion for a fast multiplier", IEEE Transactions on Elect. Computers, vol. 13, pp. 114--117, February 1964.
• 4: Niichi Itoh et al., "A 600-MHZ 54x54-bit Multiplier with Rectangular-Styled Wallace Tree", IEEE Journal of Solid-State Circuits, vol. 36, no. 2, February 2001.
• 5: O. L. McSorley, "High-Speed Arithmetic in Binary Computers", Proc. IRE, Vol. 49, pp. 67--71, January 1961.
• 6: Kiamal Z. Pekmestzi, Multiplexer-Based Array Multipliers, IEEE Transactions on Computers, v.48 n.1, p.15-23, January 1999 [doi>10.1109/12.743408]
• 7: Osama Al-Khaleel , Chris Papachristou , Frank Wolff , Kiamal Pekmestzi, A Large Scale Adaptable Multiplier for Cryptographic Applications, Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems, p.477-484, June 15-18, 2006 [doi>10.1109/AHS.2006.6]
• 8: S. Nakamura , K. -Y. Chu, A Single Chip Parallel Multiplier by MOS Technology, IEEE Transactions on Computers, v.37 n.3, p.274-282, March 1988 [doi>10.1109/12.2164]
• 9: Ki-seon Cho , Jong-on Park , Jin-seok Hong , Goang-seog Choi, 54x54-bit radix-4 multiplier based on modified booth algorithm, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA [doi>10.1145/764808.764869]
• 10: Zhijun Huang , Milos D. Ercegovac, High-Performance Low-Power Left-to-Right Array Multiplier Design, IEEE Transactions on Computers, v.54 n.3, p.272-283, March 2005 [doi>10.1109/TC.2005.51]
• 11: Wen-Chang Yeh , Chein-Wei Jen, High-Speed Booth Encoded Parallel Multiplier Design, IEEE Transactions on Computers, v.49 n.7, p.692-701, July 2000 [doi>10.1109/12.863039]
• 12: Leonardo L. de Oliveira et al., "Array Hybrid Multiplier versus Modified-Booth Multiplier: Comparing Area and Power Consumption of Layout Implementations of Signed Radix-4 Architectures", Proceedings of the 47--th MWSCAS, July 25--28, 2004, Hiroshima, Japan.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.m MISCELLANEOUS

Additional Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.4 High-speed Arithmetic

General Terms:
Algorithms, Design, Performance

Keywords:
array multiplier, modified booth, multiplexer-based, radix-4 multiplier