Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits

ABSTRACT

We present an algorithm for reducing large VLSI circuits to much smaller ones with similar input-output behavior. A key feature of our method, called generic subspace, is that it is capable of reducing linear time-varying systems. This enables it to capture frequency-translation and sampling behavior, important in communication subsystems such as mixers, RF components and switched-capacitor filters. Reduction is obtained by projecting the original system described by linear differential equations into subspace of a lower dimension. Experiments have been carried out using Cadence Design Simulator which indicates that the proposed sub-space technique achieves more % reduction with less CPU time than the other model order reduction techniques existing in literature. We also present applications to RF circuit subsystems, obtaining size reductions and evaluation speedups of orders of magnitude with insignificant loss of accuracy.

REFERENCES

• 1: L. T. Pillage et.al, "Asymptotic waveform evaluation for timing analysis," IEEE TCAD, vol. 9, pp. 352--366, Apr. 1990.
• 2: E. Chiprout et.al, "Analysis of interconnect networks using complex frequency hopping (CFH)," IEEE TCAD, vol. 14, pp. 186--200, Feb. 1995.
• 3: J. E. Bracken et.al "Interconnect simulation with asymptotic waveform evaluation (AWE)," IEEE TCAS, vol. 39, pp. 869--878, Nov. 1992.
• 4: Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, PRIMA: passive reduced-order interconnect macromodeling algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.58-65, November 09-13, 1997, San Jose, California, United States
• 5: I. M. Elfadel , David D. Ling, A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.66-71, November 09-13, 1997, San Jose, California, United States
• 6: Q. Yu, et.al "Multipoint multiport algorithm for passive reduced-order model of interconnect networks," in Proc. ISCAS, vol. 6, Sept. 1998, pp. 74--77.
• 7: Pavan, et.al, "Simulation of High-Speed Distributed Interconnects Using Krylov-Space Techniques" IEEE TCAD, Vol. 19, No. 7, pp. 799--808, July 2000.
• 8: Yayun Wan , Jaijeet Roychowdhury, Operator-based model-order reduction of linear periodically time-varying systems, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065684]
• 9: J. R. Phillips, "Projection-based approaches for model reduction of weakly nonlinear, time-varying systems," IEEE TCAD, vol. 22, pp. 171--187, Feb. 2003.
• 10: E. Gad , M. Nakhla, Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function, Proceedings of the conference on Design, automation and test in Europe, p.916, March 04-08, 2002
• 11: L. Zadeh, "Frequency Analysis of Variable Networks", IRE Proc., vol. 38, pp. 291--299, 1950.
• 12: H. D''angelo, LTV Systems: Analysis and Synthesis, Allyn and Bacon, Boston, MA, 1970.
• 13: E. Gad , M. Nakhla, Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function, Proceedings of the conference on Design, automation and test in Europe, p.916, March 04-08, 2002
• 14: I.M. Jaimoukha, et.al, "Numerical solution of large scale Lyapunov equations using Krylov subspace methods", in Proc. of the 31st Conf. on Deci. and Cont., Arizona, December 1992, pp. 1927--1932.
• 15: Joel R. Phillips, Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.96-102, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288583]
• 16: Wai-Shing Lukl et.al "Waveform Krylov subspace Methods for Tightly Coupled Systems? in Proc. of ISCAS" 1996, pp. 536--539.
• 17: Guoyong Shi, et.al, "On Symbolic Model Order Reduction", IEEE TCAD, Vol. 25, No. 7, pp. 1257--1272, July 2006.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

General Terms:
Design

Keywords:
krylov subspace techniques, model order reduction, monte-carlo simulation, rlc