Compressor trees for decimal partial product reduction

ABSTRACT

Decimal multiplication has grown in interest due to the recent announcement of new IEEE 754R standards and the availability of high-speed decimal computation hardware. Prior research enabled partial products to be coded more efficiently for their use in radix 10 architectures. This paper clarifies previous techniques for partial product reduction using carry-save adders and presents a new 4:2 compressor structure. This new structure improves performance at the expense of more gates, however, regularity is introduced into the circuit to promote implementations in Very Large Scale Integration (VLSI) Designs. Results are presented and compared for several designs using a TSMC SCN6M $0.18 mu m feature size.

REFERENCES

• 1: John L. Hennessy , David A. Patterson, Computer Architecture, Fourth Edition: A Quantitative Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2006
• 2: Eric M. Schwarz, Decimal Multiplication with Efficient Partial Product Generation, Proceedings of the 17th IEEE Symposium on Computer Arithmetic, p.21-28, June 27-29, 2005 [doi>10.1109/ARITH.2005.15]
• 3: M. D. Ercegovac and T. Lang, Digital Computer Arithmetic. \newblock Elsevier/Morgan Kaufmann Publishers, 2004.
• 4: E. L. Braun, Digital Computer Design, Logic Circuitry, Synthesis. \newblock New York, N.Y.: Academic Press, 1963.
• 5: A. Weinberger, "4:2 Carry-Save Adder Module," IBM Technical Disclosure Bulletin, vol. 23, 1981.
• 6: R. K. Richards, Arithmetic Operations in Digital Computers. \newblock Princton, N.J.: D. Van Nostrand Company, Inc., 1955.
• 7: Alvaro Vazquez , Elisardo Antelo , Paolo Montuschi, A New Family of High.Performance Parallel Decimal Multipliers, Proceedings of the 18th IEEE Symposium on Computer Arithmetic, p.195-204, June 25-27, 2007 [doi>10.1109/ARITH.2007.6]
• 8: L. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349--356, 1965.
• 9: James E. Stine , Johannes Grad , Ivan Castellanos , Jeff Blank , Vibhuti Dave , Mallika Prakash , Nick Iliev , Nathan Jachimiec, A Framework for High-Level Synthesis of System-on-Chip Designs, Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education, p.67-68, June 12-13, 2005 [doi>10.1109/MSE.2005.8]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.4 High-speed Arithmetic
          Subjects: Cost/performance

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware

General Terms:
Algorithms, Design, Performance

Keywords:
VLSI, decimal arithmetic