A novel test-data compression technique using application-aware bitmask and dictionary selection methods

ABSTRACT

Higher circuit densities in System-on-Chip (SOC) designs have led to enhancement in the test data volume. Larger test data size demands not only greater memory requirements, but also an increase in the testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. This paper proposes a novel test data compression technique using bitmasks which provides a significant enhancement in the compression efficiency without introducing any additional decompression penalty. The major contributions of this paper are as follows: i) it develops an efficient bitmask selection technique for test data in order to create maximum matching patterns; ii) it develops an efficient dictionary selection method which takes into account the speculated results of compressed codes and iii) it proposes a suitable code compression technique using dictionary and bitmask based code compression that can reduce the memory and time requirements. We have used our algorithm on various test data sets and compared our results with other existing test compression techniques. Our algorithm outperforms the best known existing compression technique up to 30%, giving a best possible compression of 92.2%.

REFERENCES

• 1: Andrew Wolfe , Alex Chanin, Executing compressed programs on an embedded RISC architecture, Proceedings of the 25th annual international symposium on Microarchitecture, p.81-91, December 01-04, 1992, Portland, Oregon, United States
• 2: Anshuman Chandra , Krishnendu Chakrabarty, Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression, Proceedings of the 19th IEEE VLSI Test Symposium, p.42, March 29-April 03, 2001
• 3: A. Chandra and K. Chakrabarty, System on a chip test data compression and decompression architectures based on golomb codes. IEEE Transactions on Computer Aided Design, 20: 355--368, 2001.
• 4: Abhijit Jas , Nur A. Touba, Test vector decompression via cyclical scan chains and its application to testing core-based designs, Proceedings of the 1998 IEEE International Test Conference, p.458-464, October 18-22, 1998
• 5: Charles Lefurgy , Peter Bird , I-Cheng Chen , Trevor Mudge, Improving code density using compression techniques, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.194-203, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 6: Chang Hong Lin , Yuan Xie , Wayne Wolf, LZW-Based Code Compression for VLIW Embedded Systems, Proceedings of the conference on Design, automation and test in Europe, p.30076, February 16-20, 2004
• 7: H. Lekatsas and W. Wolf. SAMC: A code compression algorithm for embedded processors. IEEE Transactions on Computer--Aided Design of Integrated Circuits and Systems, 18(12): 1689--1701, December 1999.
• 8: http://www.ibm.com. CodePack PowerPC Code Compression Utility User's Manual. Version 3.0, 1998.
• 9: Ilker Hamzaoglu , Janak H. Patel, Test set compaction algorithms for combinational circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.283-289, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288615]
• 10: J. Prakash , C. Sandeep , Priti Shankar , Y. N. Srikant, A Simple and Fast Scheme for Code Compression for VLIW Processors, Proceedings of the Conference on Data Compression, p.444, March 25-27, 2003
• 11: Lei Li , Krishnendu Chakrabarty , Nur A. Touba, Test data compression using dictionaries with selective entries and fixed-length indices, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.4, p.470-490, October 2003 [doi>10.1145/944027.944032]
• 12: Montserrat Ros , Peter Sutton, A hamming distance based VLIW/EPIC code compression technique, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA [doi>10.1145/1023833.1023853]
• 13: N. Ishiura and M. Yamaguchi. Instruction code compression for application specific VLIW processors based on automatic field partitioning. In Proceedings of Synthesis and System Integration of Mixed Technologies (SASIMI), pages 105--109, 1997.
• 14: P. Gonciari , B. Al-Hashimi , N. Nicolici, Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression, Proceedings of the conference on Design, automation and test in Europe, p.604, March 04-08, 2002
• 15: S. Y. Liao , S. Devadas , K. Keutzer, Code density optimization for embedded DSP processors using data compression techniques, Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95), p.272, March 27-29, 1995
• 16: S. Nam, I. Park and C. Kyung. Improving dictionary-based compression in VLIW architectures. IEICE Transactions Fundamentals, E82-A(11):2318--2324, November 1999.
• 17: Seok-Won Seong , Prabhat Mishra, An efficient code compression technique using application-aware bitmask and dictionary selection methods, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
• 18: Vikram Iyengar , Krishnendu Chakrabarty , Brian T. Murray, Deterministic Built-in Pattern Generation for Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.97-114, August-October 1999 [doi>10.1023/A:1008384201996]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Reliability, Verification

Keywords:
compression, decompression, test data